A neural-network approach to recognize defect spatial pattern in semiconductor fabrication

FL Chen, SF Liu - IEEE transactions on semiconductor …, 2000 - ieeexplore.ieee.org
Yield enhancement in semiconductor fabrication is important. Even though IC yield loss may
be attributed to many problems, the existence of defects on the wafer is one of the main …

A neural-network approach for semiconductor wafer post-sawing inspection

CT Su, T Yang, CM Ke - IEEE Transactions on semiconductor …, 2002 - ieeexplore.ieee.org
Semiconductor wafer post-sawing requires full inspection to assure defect-free outgoing
dies. A defect problem is usually identified through visual judgment by the aid of a scanning …

Wafer defect recognition method based on multi-scale feature fusion

Y Chen, M Zhao, Z Xu, K Li, J Ji - Frontiers in Neuroscience, 2023 - frontiersin.org
Wafer defect recognition is an important process of chip manufacturing. As different process
flows can lead to different defect types, the correct identification of defect patterns is …

Yield learning and the sources of profitability in semiconductor manufacturing and process development

C Weber - IEEE Transactions on Semiconductor Manufacturing, 2004 - ieeexplore.ieee.org
A numerical model that identifies the high-leverage variables associated with profitability in
semiconductor manufacturing is presented. Varying the parameters of the model …

[PDF][PDF] Inspection in semiconductor manufacturing

KW Tobin - Webster's Encyclopedia of Electrical and Electronic …, 1999 - Citeseer
In-line microscopy must keep up with the flow of manufacturing. At an inspection point, of
which there are several in the process stream, a fraction of the wafers will be inspected …

A neural-network approach for defect recognition in TFT-LCD photolithography process

LF Chen, CT Su, MH Chen - IEEE transactions on electronics …, 2009 - ieeexplore.ieee.org
Since the advent of high qualification and tiny technology, yield control in the
photolithography process has played an important role in the manufacture of thin-film …

Use of short-loop electrical measurements for yield improvement

C Yu, T Maung, CJ Spanos, DS Boning… - IEEE transactions on …, 1995 - ieeexplore.ieee.org
Modern submicron processes are more sensitive to both random and systematic wafer-level
process variation than ever before. Given the dimensional control limitations of new …

Hybrid machine learning system for integrated yield management in semiconductor manufacturing

BS Kang, JH Lee, CK Shin, SJ Yu, SC Park - Expert Systems with …, 1998 - Elsevier
Yield is one of the most important indices determining the success in semiconductor
manufacturing business. Previous yield management efforts are to enhance yield of the …

Enabling collaborative solutions across the semiconductor manufacturing ecosystem

J Yang, CM Weber, P Gabella - IEEE transactions on …, 2013 - ieeexplore.ieee.org
A qualitative empirical study of 29 semiconductor manufacturer and supplier firms
investigates the challenges associated with implementing lean practices that require broadly …

Maintenance scheduling of plasma etching chamber in wafer fabrication for high-yield etching process

CM Tan, M Luo, ICH Leng - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Plasma etching is commonly employed in the chemical etching process of wafer fabrication
because of its low cost and good control of etching profile and uniformity. In the plamas …