This article overviews the design considerations and state-of-the-art of the ring voltage-
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-Nmultiplying delay-
locked loop (MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed …

This article presents a low jitter, low power, low reference spur LC oscillator-based reference
oversampling digital phase locked loop (OSPLL). The proposed reference oversampling …

This article presents a low-power fractional-all-digital phase-locked loop (ADPLL) employing
a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective …

This article presents an injection-locked (IL) ring-oscillator-based fractional-digital phase
locked loop (DPLL) supporting Bluetooth low energy (BLE) frequency modulation with an …

This work presents a low-jitter, low-reference-spur ring voltage-controlled oscillator (ring
VCO)-based injection-locked clock multiplier (ILCM). Since the proposed triple-point …

This article presents a wide-lock-in-range and ultralow-jitter, 12–14.5 GHz subsampling
phase-locked loop (SSPLL) using a frequency-disturbance-detecting/correcting (FDC) loop …

A phase-locked loop (PLL) employing a split-feedback divider and nested-PLL-based phase-
domain low-pass filter (PDLPF) within the harmonic-mixer (HM)-based dual-feedback …

This work presents an ultralow-jitter ring-oscillator (RO)-based injection-locked clock
multiplier (ILCM). Using the power-gating (PG) injection method that can completely remove …

A ring oscillator (RO) generates a multi-phase clock with a large tuning range in a small
area, enabling a per-lane implementation in multilane communication applications …