Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

I Ferain, CA Colinge, JP Colinge - Nature, 2011‏ - nature.com
For more than four decades, transistors have been shrinking exponentially in size, and
therefore the number of transistors in a single microelectronic chip has been increasing …

Review of the nanoscale FinFET device for the applications in nano-regime

SU Haq, VK Sharma - Current Nanoscience, 2023‏ - benthamdirect.com
Background: The insatiable need for low-power and high-performance integrated circuit (IC)
results in the development of alternative options for metal oxide semiconductor field effect …

Junctionless multiple-gate transistors for analog applications

RT Doria, MA Pavanello, RD Trevisoli… - … on Electron Devices, 2011‏ - ieeexplore.ieee.org
This paper presents the evaluation of the analog properties of nMOS junctionless (JL)
multigate transistors, comparing their performance with those exhibited by inversion-mode …

A comprehensive analysis of junctionless tri-gate (TG) FinFET towards low-power and high-frequency applications at 5-nm gate length

VB Sreenivasulu, V Narendar - Silicon, 2021‏ - Springer
Abstract Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate
lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless …

RF performance and small-signal parameter extraction of junctionless silicon nanowire MOSFETs

S Cho, KR Kim, BG Park… - IEEE Transactions on …, 2011‏ - ieeexplore.ieee.org
This paper presents a radio-frequency (RF) model and extracted model parameters for
junctionless silicon nanowire (JLSNW) metal-oxide-semiconductor field-effect transistors …

Design and investigation of the 22 nm FinFET based dynamic latched comparator for low power applications

K Sarangam, AS Kumar, BNK Reddy - Transactions on Electrical and …, 2024‏ - Springer
A low-power, high-speed two-stage dynamic latch comparator suitable for high-resolution
analog-to-digital converters (ADCs) is described and implemented in this work using 22 nm …

Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length

VB Sreenivasulu, V Narendar - AEU-International Journal of Electronics …, 2021‏ - Elsevier
In this paper, for the first time, we have investigated the DC and analog/RF performance
metrics of 3 nm gate length (LG) silicon-on-insulator (SOI) FinFET using Hf x Ti 1− x O 2 high …

A 4-GS/s 10-ENOB 75-mW ringamp ADC in 16-nm CMOS with background monitoring of distortion

B Hershberg, D Dermit, B van Liempd… - IEEE Journal of Solid …, 2021‏ - ieeexplore.ieee.org
A interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages
the performance advantages of ring amplifiers to unlock greater architectural freedom. The …

Molecular layer deposition of hybrid silphenylene-based dielectric film

X Li, M Vehkamäki, M Chundak, K Mizohata… - … Composites and Hybrid …, 2023‏ - Springer
Molecular layer deposition (MLD) offers molecular level control in deposition of organic and
hybrid thin films. This article describes a new type of inorganic–organic silicon-based MLD …