DPCS: Dynamic power/capacity scaling for SRAM caches in the nanoscale era

M Gottscho, A BanaiyanMofrad, N Dutt… - ACM Transactions on …, 2015 - dl.acm.org
Fault-Tolerant Voltage-Scalable (FTVS) SRAM cache architectures are a promising
approach to improve energy efficiency of memories in the presence of nanoscale process …

A fault-tolerant last level cache for CMPs operating at ultra-low voltage

A Ferrerón, J Alastruey-Benedé, DS Gracia… - Journal of Parallel and …, 2019 - Elsevier
Voltage scaling to values near the threshold voltage is a promising technique to hold off the
many-core power wall. However, as voltage decreases, some SRAM cells are unable to …

[책][B] Opportunistic memory systems in presence of hardware variability

MW Gottscho - 2017 - search.proquest.com
The memory system presents many problems in computer architecture and system design.
An important challenge is worsening hardware variability that is caused by nanometer-scale …

Modeling & analysis of redundancy based fault tolerance for permanent faults in chip multiprocessor cache

A Choudhury, BK Sikdar - … on VLSI Design and 2018 17th …, 2018 - ieeexplore.ieee.org
With increased number of cores in Multicore Chips, power consumption raises. Voltage
scaling is applied largely but it causes cell failure in cache. For that, various techniques for …

Characterizing fault propagation in safety-critical processor designs

J Espinosa, C Hernandez… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
Achieving reduced time-to-market in modern electronic designs targeting safety critical
applications is becoming very challenging, as these designs need to go through a …

CORE-VR: A Coherence and Reusability Aware Low Voltage Fault Tolerant Cache in Multicore

A Choudhury, BK Sikdar - … on Defect and Fault Tolerance in …, 2019 - ieeexplore.ieee.org
Voltage scaling to reduce power consumption for ensuring longer battery life expedites
SRAM cell failures due to process variations. Cache, holding significant chip area …

Modeling Remap** Based Fault Tolerance Techniques for Chip Multiprocessor Cache with Design Space Exploration

A Choudhury, BK Sikdar - Journal of Electronic Testing, 2020 - Springer
On top of the wear-out failures and external particle interventions, voltage scaling to mitigate
the power consumption in multiprocessor makes cache more vulnerable to cell failures. For …

Towards certification-aware fault injection methodologies using virtual prototypes

J Espinosa, D de Andrés, JC Ruiz… - FDL 2015 …, 2015 - upcommons.upc.edu
Safety-critical applications are required today to meet more and more stringent standards
than ever. In the need of reducing the costs associated with the certification step, early …

Performance Analysis of Disability Based Fault Tolerance Techniques for Permanent Faults in Chip Multiprocessors

A Choudhury, BK Sikdar - International Symposium on VLSI Design and …, 2017 - Springer
Abstract Dynamic Voltage and Frequency Scaling (DVFS) for reducing power dissipation in
Multicore Chips causes cell failure in Cache Memory. Various fault tolerance techniques …

Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection

J Espinosa, C Hernandez… - 2016 IEEE 22nd …, 2016 - ieeexplore.ieee.org
Future high-performance safety-relevant applications require microcontrollers delivering
higher performance than the existing certified ones. However, means for assessing their …