Novel integration process and performances analysis of Low STandby Power (LSTP) 3D Multi-Channel...

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Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors

WM Weber, T Mikolajick - Reports on Progress in Physics, 2017 - iopscience.iop.org
Research in the field of electronics of 1D group-IV semiconductor structures has attracted
increasing attention over the past 15 years. The exceptional combination of the unique 1D …
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Method of constructing a semiconductor device and structure

Z Or-Bach, DC Sekar, B Cronquist, I Beinglass… - US Patent …, 2012 - Google Patents
2011-12-06 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
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Multilevel semiconductor device and structure with memory

Z Or-Bach, JW Han - US Patent 10,515,981, 2019 - Google Patents
US10515981B2 - Multilevel semiconductor device and structure with memory - Google
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
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Method of forming three dimensional integrated circuit devices using layer transfer technique

Z Or-Bach, D Sekar, B Cronquist, Z Wurman - US Patent 8,642,416, 2014 - Google Patents
US8642416B2 - Method of forming three dimensional integrated circuit devices using layer
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
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Semiconductor device and structure

Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
US8362482B2 - Semiconductor device and structure - Google Patents US8362482B2 -
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
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Semiconductor device and structure

Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
2011-03-25 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
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Method for fabrication of a semiconductor device and structure

Z Or-Bach, DC Sekar, B Cronquist - US Patent 8,557,632, 2013 - Google Patents
US8557632B1 - Method for fabrication of a semiconductor device and structure - Google
Patents US8557632B1 - Method for fabrication of a semiconductor device and structure …
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Semiconductor device and structure

Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
2010-12-03 Assigned to NuPGA Corporation reassignment NuPGA Corporation
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
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Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET

Y Choi, K Lee, KY Kim, S Kim, J Lee, R Lee… - Solid-State …, 2020 - Elsevier
By using technology computer aided design (TCAD) simulation, the aim of this paper is to
investigate the effect of Si parasitic channel, which is placed under stacked nanosheet …
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Semiconductor system and device

Z Or-Bach, D Sekar, B Cronquist, Z Wurman - US Patent 9,219,005, 2015 - Google Patents
US9219005B2 - Semiconductor system and device - Google Patents US9219005B2 -
Semiconductor system and device - Google Patents Semiconductor system and device …
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