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Equalization in high-speed communication systems
J Liu, X Lin - IEEE Circuits and Systems Magazine, 2004 - ieeexplore.ieee.org
The article first discusses the major non-ideal issues of low-cost transmission media for over
Gbps data transmissions-the frequency dispersion loss and channel noise. The former …
Gbps data transmissions-the frequency dispersion loss and channel noise. The former …
Analogue adaptive filters: past and present
Analogue adaptive filters represent an important niche in adaptive-filter theory and practice.
The paper provides an overview of the field. Important adaptive algorithms, filter structures …
The paper provides an overview of the field. Important adaptive algorithms, filter structures …
A CMOS 0.25-/spl mu/m continuous-time FIR filter with 125 ps per tap delay as a fractionally spaced receiver equalizer for 1-gb/s data transmission
X Lin, S Saw, J Liu - IEEE journal of solid-state circuits, 2005 - ieeexplore.ieee.org
This paper presents a CMOS 0.25-/spl mu/m continuous-time 6-tap FIR filter that is used as a
fractionally spaced receiver equalizer for 1-Gb/s data transmission. Each tap of the FIR filter …
fractionally spaced receiver equalizer for 1-Gb/s data transmission. Each tap of the FIR filter …
FIR filter architecture for 100Base-TX receiver
G Chou, GC Tai - US Patent 6,614,842, 2003 - Google Patents
(57) ABSTRACT A 100Base-TX receiver employs a? nite impulse response (FIR)? lter to
provide both equalization and insertion loss compensation for an MLT-3 input signal. The …
provide both equalization and insertion loss compensation for an MLT-3 input signal. The …
Efficient digital baseline wander algorithm and its architecture for fast ethernet
JH Baek, JH Hong, MH Sunwoo… - … Systems, 2004. SIPS …, 2004 - ieeexplore.ieee.org
The paper proposes an efficient digital baseline wander (BLW) algorithm and its hardware
architecture for 100BASE-TX Ethernet. The proposed BLW compensator uses four symbols …
architecture for 100BASE-TX Ethernet. The proposed BLW compensator uses four symbols …
A 3 V low-power 0.25/spl mu/m CMOS 100 Mb/s receiver for Fast Ethernet
O Shoaei, A Shoval… - 2000 IEEE International …, 2000 - ieeexplore.ieee.org
A transceiver with excellent performance was recently reported. However, a higher level of
integration for multi-channel transceivers for switch application and also for battery-operated …
integration for multi-channel transceivers for switch application and also for battery-operated …
Low power analogue equaliser with adaptive digital tuning for fast ethernet
This work presents an analogue equaliser with digital tuning. It compensates the losses
introduced by up to 120 m long category 5 unshielded twisted pair cables and baseline …
introduced by up to 120 m long category 5 unshielded twisted pair cables and baseline …
A low-power gigabit Ethernet analog equalizer
P Amini, O Shoaei - ISCAS 2001. The 2001 IEEE International …, 2001 - ieeexplore.ieee.org
An analog continuous time digitally adaptive cable equalizer for gigabit Ethernet has been
designed in a 0.35/spl mu/m CMOS process with a single 3 V supply. A three-stage opamp …
designed in a 0.35/spl mu/m CMOS process with a single 3 V supply. A three-stage opamp …
A 2V low-power CMOS 125Mbaud repeater architecture for UTP5 cables
A repeater has been developed for 125Mbaud twisted pair data communication with binary
signal levels. The repeater includes an adaptive equalizer and a driver. This architecture …
signal levels. The repeater includes an adaptive equalizer and a driver. This architecture …
A low power and small area analog adaptive line equalizer for 100 Mb/s data rate on UTP cable
The cable length in wired serial data communication is limited because the limited
bandwidth of a long cable introduces ISI (Inter Symbol Interference). A line equalizer can be …
bandwidth of a long cable introduces ISI (Inter Symbol Interference). A line equalizer can be …