[HTML][HTML] Time-to-digital conversion techniques: a survey of recent developments

J Szyduczyński, D Kościelnik, M Miśkowicz - Measurement, 2023 - Elsevier
Time-to-digital converters (TDCs) are key components of time-mode circuits and enablers for
digital processing of analog signals encoded in time. Since design of time-mode circuits …

Recent advances and trends in voltage-time domain hybrid ADCs

Y Zhang, Z Zhu - IEEE Transactions on Circuits and Systems II …, 2022 - ieeexplore.ieee.org
The benefits of technology scaling have fueled interest in voltage-time domain hybrid ADCs.
The hybrid ADCs employing combinations of successive approximation register (SAR), time …

A 7 bit, 3.75 ps resolution two-step time-to-digital converter in 65 nm CMOS using pulse-train time amplifier

KS Kim, YH Kim, WS Yu, SH Cho - IEEE Journal of Solid-State …, 2013 - ieeexplore.ieee.org
In this paper, a novel pulse-train time amplifier is proposed that achieves linear, accurate,
and programmable gain for a wide input range. Using the proposed pulse-train time …

A 9 bit, 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register

KS Kim, W Yu, SH Cho - IEEE Journal of Solid-State Circuits, 2014 - ieeexplore.ieee.org
In this paper, a 2.5 b/stage pipelined time-to-digital converter (TDC) is presented. For
pipelined operation, a novel time-register is proposed which is capable of storing, adding …

A miniature 2 mW 4 bit 1.2 GS/s delay-line-based ADC in 65 nm CMOS

YM Tousi, E Afshari - IEEE Journal of Solid-State Circuits, 2011 - ieeexplore.ieee.org
A delay-line-based analog-to-digital converter for high-speed applications is introduced. The
ADC converts the sampled input voltage to a delay that controls the propagation velocity of a …

A time-based pipelined ADC using both voltage and time domain information

T Oh, H Venkatram, UK Moon - IEEE Journal of Solid-State …, 2013 - ieeexplore.ieee.org
In this paper, a Nyquist ADC with a time-based pipelined TDC is proposed. In the proposed
ADC, the first pipeline stage incorporates both residue amplification and a VT conversion …

5-bit 5-GS/s noninterleaved time-based ADC in 65-nm CMOS for radio-astronomy applications

Y Xu, G Wu, L Belostotski… - IEEE Transactions on Very …, 2016 - ieeexplore.ieee.org
This paper presents a 5-bit noninterleaved time-based analog-to-digital converter (ADC),
which operates at a 5-GS/s rate. The ADC is designed for the use in radio-astronomy …

Constraint handling in combinatorial test generation using forbidden tuples

L Yu, F Duan, Y Lei, RN Kacker… - 2015 IEEE Eighth …, 2015 - ieeexplore.ieee.org
Constraint handling is a challenging problem in combinatorial test generation. In general,
there are two ways to handle constraints, ie, constraint solving and forbidden tuples. In our …

[BUCH][B] CMOS time-mode circuits and systems: fundamentals and applications

F Yuan - 2018 - books.google.com
Time-mode circuits, where information is represented by time difference between digital
events, offer a viable and technology-friendly means to realize mixed-mode circuits and …

Fully integrated digital average current-mode control voltage regulator module IC

E Abramov, T Vekslender… - IEEE journal of …, 2017 - ieeexplore.ieee.org
This paper introduces a fully integrated 12-to-1. xV voltage regulator module IC. A fully
synthesizable digital two-loop controller has been realized through hardware description …