Substrate noise issues are a showstopper for the smooth integration of analog and digital
circuitries on the same die. For the designer, it is not known how substrate noise couples …

Substrate noise problems in a system-on-a-chip hamper the smooth cohabitation between
analog and digital circuitries on the same die. Solving those problems will shorten the time …

Board-level I/Os signal integrity and conducted EMI have become a critical concern for high-
speed circuit and package designers, and a major element of performance and reliability …

This paper presents the noise isolation characteristics and substrate loading effects of
NMOS devices in triple-well (TW) at frequencies up to 50 GHz. The importance of the series …

Experimental measurements of the isolation provided by N and P-type rings, and triple-well
structures implemented in 0.35¿ m and 0.18¿ m technologies are presented. The results …

This paper presents the characterization of substrate noise coupling and the isolation
capability of ohmic substrate contacts in a HV CMOS technology. Layout variations of …

Substrate noise problems continue to harass the design of a System-on-a-Chip (SoC). It is
not obvious for the designer to identify the dominant substrate noise entry points. This paper …

The semiconductor industry has maintained technology scaling at the pace of Moore's Law
for the past 50 years [1, 2]. The feature size of transistors scales by a factor of 0.7 every three …

In the large-scale high energy physics experiments multi-channel readout application
specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are …

In the past years, integration levels in electronic systems have been continuously increasing
so as to enable the development of high-performance products and applications [1, 2]. This …