Turnitin
降AI改写
早检测系统
早降重系统
Turnitin-UK版
万方检测-期刊版
维普编辑部版
Grammarly检测
Paperpass检测
checkpass检测
PaperYY检测
An efficient hardware architecture of integer motion estimation based on early termination and data reuse for Versatile video coding
J Zhang, Y Zhang, H Zhang - Expert Systems with Applications, 2024 - Elsevier
The integer motion estimation (IME) involves high computational complexity and large
amount of computation data due to the variable block sizes, and it is one of the most critical …
amount of computation data due to the variable block sizes, and it is one of the most critical …
An approximate versatile video coding fractional interpolation hardware
In this paper, approximate Versatile Video Coding (VVC) fractional interpolation filters are
proposed. They significantly reduce computational complexity of VVC fractional interpolation …
proposed. They significantly reduce computational complexity of VVC fractional interpolation …
A low power versatile video coding (VVC) fractional interpolation hardware
Fractional interpolation in Versatile Video Coding (VVC) standard has much higher
computational complexity than fractional interpolation in previous video compression …
computational complexity than fractional interpolation in previous video compression …
A reconfigurable fractional interpolation hardware for VVC motion compensation
Fractional interpolation is one of the most computationally complex parts of video
compression standards. Fractional interpolation in Versatile Video Coding (VVC) standard …
compression standards. Fractional interpolation in Versatile Video Coding (VVC) standard …
Effective hardware accelerator for 2d dct/idct using improved loeffler architecture
Z Zhou, Z Pan - IEEE Access, 2022 - ieeexplore.ieee.org
This paper proposes an effective hardware accelerator for 2D discrete cosine transform
(DCT) and inverse discrete cosine transform (IDCT) using an improved Loeffler architecture …
(DCT) and inverse discrete cosine transform (IDCT) using an improved Loeffler architecture …
An efficient FPGA implementation of HEVC intra prediction
Intra prediction algorithm used in High Efficiency Video Coding (HEVC) standard has very
high computational complexity. In this paper, an efficient FPGA implementation of HEVC …
high computational complexity. In this paper, an efficient FPGA implementation of HEVC …
Reconfigurable intra prediction hardware for future video coding
In this paper, two Future Video Coding (FVC) reconfigurable intra prediction hardware are
proposed. They are the first FVC intra prediction hardware in the literature. The first …
proposed. They are the first FVC intra prediction hardware in the literature. The first …
Efficient 2D transform hardware architecture for the versatile video coding standard
Q Sheng, R Pan, J Chen, C Lai, Y Liu, X Huang… - Journal of Visual …, 2024 - Elsevier
As the latest generation of video coding standards, versatile video coding (VVC) introduces
several new coding tools in transform coding to concentrate the energy of residual blocks. In …
several new coding tools in transform coding to concentrate the energy of residual blocks. In …
Hardware architecture optimization for high-frequency zeroing and LFNST in H. 266/VVC based on FPGA
J Zhang, Q Sheng, R Pan, J Wang, K Qin… - Journal of Real-Time …, 2024 - Springer
To reduce the hardware implementation resource consumption of the two-dimensional
transform component in H. 266 VVC, a unified hardware structure is proposed that supports …
transform component in H. 266 VVC, a unified hardware structure is proposed that supports …
Hardware efficient architecture for 2D DCT and IDCT using Taylor-series expansion of trigonometric functions
This paper presents a hardware architecture for 8 x 8 2D Discrete Cosine Transform (DCT)
and Inverse DCT (IDCT) using Taylor-series expansion of trigonometric functions. The …
and Inverse DCT (IDCT) using Taylor-series expansion of trigonometric functions. The …