Multi-threshold voltage (Vt) workfunction metal by selective atomic layer deposition (ALD)

A Brand, N Yoshida, S Ganguli, D Thompson… - US Patent …, 2018 - Google Patents
Methods for forming a multi-threshold voltage device on a substrate are provided herein. In
some embodiments, the method of forming a multi-threshold voltage device may include (a) …

FinFET/tri-gate channel do** for multiple threshold voltage tuning

Y Zhang, Z Fang, JJ Xu - US Patent 8,853,025, 2014 - Google Patents
An embodiment method of controlling threshold voltages in a fin field effect transistor
(FinFET) includes forming a dummy gate over a central portion of a fin, the central portion of …

Numerical investigation of short-channel effects in negative capacitance MFIS and MFMIS transistors: Subthreshold behavior

G Pahwa, A Agarwal… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
We present a detailed TCAD analysis of the impact of length scaling and the associated
short-channel effects in the subthreshold regime of the two classes of double-gate negative …

One-sided schmitt-trigger-based 9T SRAM cell for near-threshold operation

K Cho, J Park, TW Oh, SO Jung - IEEE Transactions on Circuits …, 2020 - ieeexplore.ieee.org
This paper presents a one-sided Schmitt-trigger-based 9T static random access memory cell
with low energy consumption and high read stability, write ability, and hold stability yields in …

Fin shape impact on FinFET leakage with application to multithreshold and ultralow-leakage FinFET design

BD Gaynor, S Hassoun - IEEE Transactions on Electron …, 2014 - ieeexplore.ieee.org
FinFETs have emerged as the solution to short channel effects at the 22-nm technology
node and beyond. Previously, there have been few studies on the impact of fin cross section …

Design and analysis of gate stack silicon-on-insulator nanosheet FET for low power applications

R Yuvaraj, A Karuppannan, AK Panigrahy, R Swain - Silicon, 2023 - Springer
Since the introduction of fast integrated circuits, semiconductor manufacturers have
concentrated their efforts on reducing the size of transistors. Increased working frequencies …

Statistical timing analysis considering device and interconnect variability for BEOL requirements in the 5-nm node and beyond

T Huynh-Bao, J Ryckaert, Z Tőkei… - … Transactions on Very …, 2017 - ieeexplore.ieee.org
In an increasing interconnect resistance era and aggressive metal pitch scaling, the
elevating RC delay could significantly shadow the improvements from advanced device …

Impact of back-gate biasing on the transport properties of 22 nm FD-SOI MOSFETs at cryogenic temperatures

F Al Mamun, D Vasileska… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This article reports on the impact of back gate bias on the transport properties and
performance of 22 nm fully depleted silicon-on-insulator (FD-SOI) MOSFETs. FD-SOI …

CryoCache: A fast, large, and cost-effective cache architecture for cryogenic computing

D Min, I Byun, GH Lee, S Na, J Kim - Proceedings of the Twenty-Fifth …, 2020 - dl.acm.org
Cryogenic computing, which is to run a computer at extremely low temperatures (eg, 77K), is
a highly promising solution to dramatically improve the computer's performance and power …

Application of atomic force microscopy technology in do** characterization of semiconductor materials and devices

X Liu, X Wang, X Liu, Y Song, Y Zhang, H Wang… - Microelectronic …, 2024 - Elsevier
The precise characterization of the do** profile is crucial for optimizing the performance
and structural integrity of semiconductor devices. As the size of semiconductor devices …