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Ultra-low power VLSI circuit design demystified and explained: A tutorial
In this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a
unitary framework for the first time. A few general principles are first introduced to gain an …
unitary framework for the first time. A few general principles are first introduced to gain an …
Securing commercial WiFi-based UAVs from common security attacks
We posit that commercial Wi-Fi-based unmanned aerial vehicles (UAV) are vulnerable to
common and basic security attacks, capable by beginner to intermediate hackers. We do this …
common and basic security attacks, capable by beginner to intermediate hackers. We do this …
Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow‐Power Applications
In recent years, subthreshold operation has gained a lot of attention due to ultra low‐power
consumption in applications requiring low to medium performance. It has also been shown …
consumption in applications requiring low to medium performance. It has also been shown …
Utilizing reverse short channel effect for optimal subthreshold circuit design
The impact of the Reverse Short Channel Effect (RSCE) on device current is stronger in the
subthreshold region due to the reduced Drain-Induced-Barrier-Lowering (DIBL) and the …
subthreshold region due to the reduced Drain-Induced-Barrier-Lowering (DIBL) and the …
An ultra-low-energy multi-standard JPEG co-processor in 65 nm CMOS with sub/near threshold supply voltage
We present a design technique for (near) subthreshold operation that achieves ultra low
energy dissipation at throughputs of up to 100 MB/s suitable for digital consumer electronic …
energy dissipation at throughputs of up to 100 MB/s suitable for digital consumer electronic …
A 40 nm dual-width standard cell library for near/sub-threshold operation
Near/sub-threshold operation is promising to achieve energy minimization when high
performance is not required. The device sizing in sub-threshold region is different from super …
performance is not required. The device sizing in sub-threshold region is different from super …
Low voltage dual mode logic: Model analysis and parameter extraction
The Dual Model Logic (DML) family, which was recently introduced by our group for sub-
threshold operation, provides an alternative design methodology to the existing low power …
threshold operation, provides an alternative design methodology to the existing low power …
Logical effort for CMOS-based dual mode logic gates
I Levi, A Belenky, A Fish - … on very large scale integration (VLSI) …, 2013 - ieeexplore.ieee.org
Recently, a novel dual mode logic (DML) family was proposed. This logic allows operation in
two modes: 1) static and 2) dynamic modes. DML gates, which can be switched between …
two modes: 1) static and 2) dynamic modes. DML gates, which can be switched between …
Twenty years of near/sub-threshold design trends and enablement
This brief surveys the past 20 years of near/sub-threshold digital integrated circuit design.
Most of the chips have been highly characterized for voltage scaling down to near/sub …
Most of the chips have been highly characterized for voltage scaling down to near/sub …
A novel framework to estimate the path delay variability on the back of an envelope via the fan-out-of-4 metric
M Alioto, G Scotti, A Trifiletti - IEEE Transactions on Circuits and …, 2017 - ieeexplore.ieee.org
In this paper, a novel framework is introduced to estimate the max-delay variability in logic
paths due to variations in a back-of-the-envelope fashion, thus allowing quick evaluation of …
paths due to variations in a back-of-the-envelope fashion, thus allowing quick evaluation of …