A survey of microarchitectural side-channel vulnerabilities, attacks, and defenses in cryptography

X Lou, T Zhang, J Jiang, Y Zhang - ACM Computing Surveys (CSUR), 2021 - dl.acm.org
Side-channel attacks have become a severe threat to the confidentiality of computer
applications and systems. One popular type of such attacks is the microarchitectural attack …

Timing side-channel attacks and countermeasures in CPU microarchitectures

J Zhang, C Chen, J Cui, K Li - ACM Computing Surveys, 2024 - dl.acm.org
Microarchitectural vulnerabilities, such as Meltdown and Spectre, exploit subtle
microarchitecture state to steal the user's secret data and even compromise the operating …

Last-level cache side-channel attacks are practical

F Liu, Y Yarom, Q Ge, G Heiser… - 2015 IEEE symposium on …, 2015 - ieeexplore.ieee.org
We present an effective implementation of the Prime+ Probe side-channel attack against the
last-level cache. We measure the capacity of the covert channel the attack creates and …

{ScatterCache}: thwarting cache attacks via cache set randomization

M Werner, T Unterluggauer, L Giner… - 28th USENIX Security …, 2019 - usenix.org
Cache side-channel attacks can be leveraged as a building block in attacks leaking secrets
even in the absence of software bugs. Currently, there are no practical and generic …

A survey of microarchitectural timing attacks and countermeasures on contemporary hardware

Q Ge, Y Yarom, D Cock, G Heiser - Journal of Cryptographic Engineering, 2018 - Springer
Microarchitectural timing channels expose hidden hardware states though timing. We survey
recent attacks that exploit microarchitectural features in shared hardware, especially as they …

Port contention for fun and profit

AC Aldaya, BB Brumley, S ul Hassan… - … IEEE Symposium on …, 2019 - ieeexplore.ieee.org
Simultaneous Multithreading (SMT) architectures are attractive targets for side-channel
enabled attackers, with their inherently broader attack surface that exposes more per …

{FLUSH+ RELOAD}: A high resolution, low noise, l3 cache {Side-Channel} attack

Y Yarom, K Falkner - 23rd USENIX security symposium (USENIX security …, 2014 - usenix.org
Sharing memory pages between non-trusting processes is a common method of reducing
the memory footprint of multi-tenanted systems. In this paper we demonstrate that, due to a …

Cache template attacks: Automating attacks on inclusive {Last-Level} caches

D Gruss, R Spreitzer, S Mangard - 24th USENIX Security Symposium …, 2015 - usenix.org
Recent work on cache attacks has shown that CPU caches represent a powerful source of
information leakage. However, existing attacks require manual identification of …

Varys: Protecting {SGX} enclaves from practical {Side-Channel} attacks

O Oleksenko, B Trach, R Krahn, M Silberstein… - 2018 Usenix Annual …, 2018 - usenix.org
Numerous recent works have experimentally shown that Intel Software Guard Extensions
(SGX) are vulnerable to cache timing and page table side-channel attacks which could be …

CacheBleed: a timing attack on OpenSSL constant-time RSA

Y Yarom, D Genkin, N Heninger - Journal of Cryptographic Engineering, 2017 - Springer
The scatter–gather technique is a commonly implemented approach to prevent cache-based
timing attacks. In this paper, we show that scatter–gather is not constant time. We implement …