A fault tolerance technique for combinational circuits based on selective-transistor redundancy
With fabrication technology reaching nanolevels, systems are becoming more prone to
manufacturing defects with higher susceptibility to soft errors. This paper is focused on …
manufacturing defects with higher susceptibility to soft errors. This paper is focused on …
SEU tolerant SRAM cell
Modern integrated circuits require careful attention to the soft errors resulting into bit upsets,
which are normally caused by alpha particle or neutron hits. These events, also referred to …
which are normally caused by alpha particle or neutron hits. These events, also referred to …
Soft error reduction through gate input dependent weighted sizing in combinational circuits
As technology nodes are gradually shrinking, adding soft error tolerant features to logic
circuits is becoming a challenging task that requires careful consideration. Careless use of …
circuits is becoming a challenging task that requires careful consideration. Careless use of …
SEU tolerant robust memory cell design
The implementation of semiconductor circuits and systems in nano-technology makes it
possible to achieve high speed, lower voltage level and smaller area. The unintended and …
possible to achieve high speed, lower voltage level and smaller area. The unintended and …
Gate input reconfiguration for combating soft errors in combinational circuits
Many techniques to relieve soft error problem, such as making the circuit larger, called
upsizing, have been developed under tight limitation in circuit performance but they all call …
upsizing, have been developed under tight limitation in circuit performance but they all call …
On techniques for handling soft errors in digital circuits
Dealing with soft errors due to particle strikes is the next major challenge in implementing
digital systems. This study thoroughly investigates the effect of device size on circuit soft …
digital systems. This study thoroughly investigates the effect of device size on circuit soft …
Method of fault tolerance in combinational circuits
Described herein is a method implemented by circuitry for providing fault tolerance in a
combinational circuit. The circuitry identifies sensitive gates of the circuit that require …
combinational circuit. The circuitry identifies sensitive gates of the circuit that require …
Optimizing device size for soft error resilience in sub-micron logic circuits
As technology nodes are being scaled down, soft errors induced by particle strikes are
becoming a troublesome reliability issue in logic circuits. Various sizing techniques …
becoming a troublesome reliability issue in logic circuits. Various sizing techniques …
An Integrated Approach for Soft Error Tolerance of Combinational Circuits
AT Sheikh - 2016 - search.proquest.com
With fabrication technology reaching nano-scale, systems are becoming more prone to
manufacturing defects with higher susceptibility to soft errors due to the exponential …
manufacturing defects with higher susceptibility to soft errors due to the exponential …
SEU tolerant robust latch design
With the scaling of technology node and voltage levels, VLSI circuits are facing the
challenge of tolerance to soft errors normally caused by alpha particle or neutron hits. These …
challenge of tolerance to soft errors normally caused by alpha particle or neutron hits. These …