A fault tolerance technique for combinational circuits based on selective-transistor redundancy

AT Sheikh, AH El-Maleh, MES Elrabaa… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
With fabrication technology reaching nanolevels, systems are becoming more prone to
manufacturing defects with higher susceptibility to soft errors. This paper is focused on …

SEU tolerant SRAM cell

S Sarkar, A Adak, V Singh, K Saluja… - 2011 12th International …, 2011 - ieeexplore.ieee.org
Modern integrated circuits require careful attention to the soft errors resulting into bit upsets,
which are normally caused by alpha particle or neutron hits. These events, also referred to …

Soft error reduction through gate input dependent weighted sizing in combinational circuits

W Sootkaneung, KK Saluja - 2011 12th International …, 2011 - ieeexplore.ieee.org
As technology nodes are gradually shrinking, adding soft error tolerant features to logic
circuits is becoming a challenging task that requires careful consideration. Careless use of …

SEU tolerant robust memory cell design

M Shayan, V Singh, AD Singh… - 2012 IEEE 18th …, 2012 - ieeexplore.ieee.org
The implementation of semiconductor circuits and systems in nano-technology makes it
possible to achieve high speed, lower voltage level and smaller area. The unintended and …

Gate input reconfiguration for combating soft errors in combinational circuits

W Sootkaneung, KK Saluja - 2010 International Conference on …, 2010 - ieeexplore.ieee.org
Many techniques to relieve soft error problem, such as making the circuit larger, called
upsizing, have been developed under tight limitation in circuit performance but they all call …

On techniques for handling soft errors in digital circuits

W Sootkaneung, KK Saluja - 2010 IEEE International Test …, 2010 - ieeexplore.ieee.org
Dealing with soft errors due to particle strikes is the next major challenge in implementing
digital systems. This study thoroughly investigates the effect of device size on circuit soft …

Method of fault tolerance in combinational circuits

AH El-Maleh, AT Sheikh - US Patent 10,013,296, 2018 - Google Patents
Described herein is a method implemented by circuitry for providing fault tolerance in a
combinational circuit. The circuitry identifies sensitive gates of the circuit that require …

Optimizing device size for soft error resilience in sub-micron logic circuits

W Sootkaneung, KK Saluja - 2nd Asia Symposium on Quality …, 2010 - ieeexplore.ieee.org
As technology nodes are being scaled down, soft errors induced by particle strikes are
becoming a troublesome reliability issue in logic circuits. Various sizing techniques …

An Integrated Approach for Soft Error Tolerance of Combinational Circuits

AT Sheikh - 2016 - search.proquest.com
With fabrication technology reaching nano-scale, systems are becoming more prone to
manufacturing defects with higher susceptibility to soft errors due to the exponential …

SEU tolerant robust latch design

M Shayan, V Singh, AD Singh, M Fujita - Progress in VLSI Design and Test …, 2012 - Springer
With the scaling of technology node and voltage levels, VLSI circuits are facing the
challenge of tolerance to soft errors normally caused by alpha particle or neutron hits. These …