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Device with embedded high-bandwidth, high-capacity memory using wafer bonding
KN Quader, R Norman, FSK Lee, CJ Petti… - US Patent …, 2023 - Google Patents
2020-01-29 Assigned to SUNRISE MEMORY CORPORATION reassignment SUNRISE
MEMORY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT …
MEMORY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT …
3D semiconductor device and structure
Z Or-Bach, B Cronquist - US Patent 10,840,239, 2020 - Google Patents
US10840239B2 - 3D semiconductor device and structure - Google Patents US10840239B2 -
3D semiconductor device and structure - Google Patents 3D semiconductor device and …
3D semiconductor device and structure - Google Patents 3D semiconductor device and …
Semiconductor memory device and structure
Z Or-Bach, JW Han - US Patent 11,956,952, 2024 - Google Patents
A device, including: a first structure including first memory cells, the first memory cells
including first transistors; and a second structure including second memory cells, the second …
including first transistors; and a second structure including second memory cells, the second …
Wafer bonding in fabrication of 3-dimensional NOR memory circuits
SB Herner, E Harari - US Patent 11,158,620, 2021 - Google Patents
(57) ABSTRACT A memory array and single-crystal circuitry are provided by wafer bonding
(eg, adhesive wafer bonding or anodic wafer bonding) in the same integrated circuit and …
(eg, adhesive wafer bonding or anodic wafer bonding) in the same integrated circuit and …
Memory arrays with bonded and shared logic circuitry
R Fastow, K Hasnat, P Majhi, OW Jungroth… - US Patent …, 2021 - Google Patents
An integrated circuit memory includes a logic circuitry bonded to a memory array. For
example, the logic circuitry is formed separately from the memory array, and then the logic …
example, the logic circuitry is formed separately from the memory array, and then the logic …
Semiconductor memory device having a bonded circuit chip including a solid state drive controller connected to a control circuit
Y Fukuzumi, H Aochi, M Matsuo, K Yoshii… - US Patent …, 2021 - Google Patents
According to one embodiment, the array chip includes a three-dimensionally disposed
plurality of memory cells and a memory-side interconnection layer connected to the memory …
plurality of memory cells and a memory-side interconnection layer connected to the memory …
Bonded semiconductor devices having programmable logic device and NAND flash memory and methods for forming the same
W Cheng, J Liu - US Patent 11,302,700, 2022 - Google Patents
Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an
example, a semicon ductor device includes a first semiconductor structure including a …
example, a semicon ductor device includes a first semiconductor structure including a …
Bonded assembly containing memory die bonded to integrated peripheral and system die and methods for making the same
Y Zhang, Z Cui, A Nishida, J Alsmeier, Y Li… - US Patent …, 2020 - Google Patents
2019-02-19 Assigned to SANDISK TECHNOLOGIES LLC reassignment SANDISK
TECHNOLOGIES LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
TECHNOLOGIES LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
3D semiconductor device
Z Or-Bach, Z Wurman - US Patent 10,910,364, 2021 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …
Method to produce a multi-level semiconductor memory device and structure
Z Or-Bach, JW Han - US Patent 11,978,731, 2024 - Google Patents
A method to process a 3D device, the method including: providing a first substrate including
a first level including a first single crystal silicon layer and a plurality of first transistors; …
a first level including a first single crystal silicon layer and a plurality of first transistors; …