Embodiments of the invention relate to transactional memory execution utilizing virtual
memory. A processor includes a local transactional cache and a resource manager. The …

A phased transactional memory (PhTM) may support a plurality of transactional memory
implementations, including software, hardware, and hybrid implementations, and may …

7,320,065 B2 1/2008 Gosior cr 7,376,800 B1 5/2008 Choquette (*) Notice: Subject to any
disclaimer, the term of this 7,395,382 B1 7, 2008 Moir patent is extended or adjusted under …

Monitoring performance of one or more architecturally sig nificant processor caches coupled
to a processor. The meth ods include executing an application on one or more proces sors …

Methods and apparatus to provide transactional memory execution in out-of-order
processors are described. In one embodiment, a stored value corresponds to the number of …

A hardware implemented transactional memory system includes a mechanism to allow
multiple processors to access the same memory system. A set of timestamps are stored that …

6,754,773 6,775,727 6,880,045 7,114,036 7,181,608 7,188,216 7,206,903 7,822,727
8,001,538 8,225,297 2002fOO83353 2002fOO87614 2002/0091718 2004, OO15642 …

A method and apparatus for virtualizing and/or extending transactional memory is described
herein. Transactions are executed using local shared transactional memory, such as a …

A method and apparatus for efficiently executing nested transactions is herein described.
Hardware support for execution of transactions is provided. Additionally, through the use of …

BACKGROUND Advances in semi-conductor processing and logic design have permitted
an increase in the amount of logic that may be present on integrated circuit devices. As a …