Multiprocessor system-on-chip (MPSoC) technology

W Wolf, AA Jerraya, G Martin - IEEE transactions on computer …, 2008 - ieeexplore.ieee.org
The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware
subsystems to implement a system. A wide range of MPSoC architectures have been …

A Comprehensive Survey of Benchmarks for Improvement of Software's Non-Functional Properties

A Blot, J Petke - ACM Computing Surveys, 2025 - dl.acm.org
Despite recent increase in research on improvement of non-functional properties of
software, such as energy usage or program size, there is a lack of standard benchmarks for …

[BOK][B] Memory systems: cache, DRAM, disk

B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stop** your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …

[BOK][B] Design of the RISC-V instruction set architecture

AS Waterman - 2016 - search.proquest.com
The hardware-software interface, embodied in the instruction set architecture (ISA), is
arguably the most important interface in a computer system. Yet, in contrast to nearly all …

[BOK][B] Engineering a compiler

KD Cooper, L Torczon - 2022 - books.google.com
Engineering a Compiler, Third Edition covers the latest developments in compiler
technology, with new chapters focusing on semantic elaboration (the problems that arise in …

[BOK][B] Industrial communication technology handbook

R Zurawski - 2014 - books.google.com
Featuring contributions from major technology vendors, industry consortia, and government
and private research establishments, the Industrial Communication Technology Handbook …

[PDF][PDF] Frequent value compression in data caches

J Yang, Y Zhang, R Gupta - Proceedings of the 33rd annual ACM/IEEE …, 2000 - dl.acm.org
GHPQSPT QUHXSU ac SPT e S gipr H u XS vwu S y X w PXUU u HX wyiw P w cw P ipwyi
XU eyif UPS g HUP geaijklm noqrsuvr wxy {|~||{{x|{{|| x| y {|{x {y~ xy|~ yxy {| xy|{| y~|| x {y …

Warped-compression: Enabling power efficient GPUs through register compression

S Lee, K Kim, G Koo, H Jeon, WW Ro… - ACM SIGARCH …, 2015 - dl.acm.org
This paper presents Warped-Compression, a warp-level register compression scheme for
reducing GPU power consumption. This work is motivated by the observation that the …

A low-voltage processor for sensing applications with picowatt standby mode

S Hanson, M Seok, YS Lin, ZY Foo… - IEEE Journal of Solid …, 2009 - ieeexplore.ieee.org
Recent progress in ultra-low-power circuit design is creating new opportunities for cubic
millimeter computing. Robust low-voltage operation has reduced active mode power …

Frequent value locality and value-centric data cache design

Y Zhang, J Yang, R Gupta - ACM SIGARCH Computer Architecture News, 2000 - dl.acm.org
By studying the behavior of programs in the SPECint95 suite we observed that six out of
eight programs exhibit a new kind of value locality, the frequent value locality, according to …