Multiprocessor system-on-chip (MPSoC) technology
The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware
subsystems to implement a system. A wide range of MPSoC architectures have been …
subsystems to implement a system. A wide range of MPSoC architectures have been …
A Comprehensive Survey of Benchmarks for Improvement of Software's Non-Functional Properties
Despite recent increase in research on improvement of non-functional properties of
software, such as energy usage or program size, there is a lack of standard benchmarks for …
software, such as energy usage or program size, there is a lack of standard benchmarks for …
[BOK][B] Memory systems: cache, DRAM, disk
B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stop** your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
[BOK][B] Design of the RISC-V instruction set architecture
AS Waterman - 2016 - search.proquest.com
The hardware-software interface, embodied in the instruction set architecture (ISA), is
arguably the most important interface in a computer system. Yet, in contrast to nearly all …
arguably the most important interface in a computer system. Yet, in contrast to nearly all …
[BOK][B] Engineering a compiler
KD Cooper, L Torczon - 2022 - books.google.com
Engineering a Compiler, Third Edition covers the latest developments in compiler
technology, with new chapters focusing on semantic elaboration (the problems that arise in …
technology, with new chapters focusing on semantic elaboration (the problems that arise in …
[BOK][B] Industrial communication technology handbook
R Zurawski - 2014 - books.google.com
Featuring contributions from major technology vendors, industry consortia, and government
and private research establishments, the Industrial Communication Technology Handbook …
and private research establishments, the Industrial Communication Technology Handbook …
[PDF][PDF] Frequent value compression in data caches
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Warped-compression: Enabling power efficient GPUs through register compression
This paper presents Warped-Compression, a warp-level register compression scheme for
reducing GPU power consumption. This work is motivated by the observation that the …
reducing GPU power consumption. This work is motivated by the observation that the …
A low-voltage processor for sensing applications with picowatt standby mode
Recent progress in ultra-low-power circuit design is creating new opportunities for cubic
millimeter computing. Robust low-voltage operation has reduced active mode power …
millimeter computing. Robust low-voltage operation has reduced active mode power …
Frequent value locality and value-centric data cache design
By studying the behavior of programs in the SPECint95 suite we observed that six out of
eight programs exhibit a new kind of value locality, the frequent value locality, according to …
eight programs exhibit a new kind of value locality, the frequent value locality, according to …