System level analysis of fast, per-core DVFS using on-chip switching regulators

W Kim, MS Gupta, GY Wei… - 2008 IEEE 14th …, 2008 - ieeexplore.ieee.org
Portable, embedded systems place ever-increasing demands on high-performance, low-
power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well …

Voltage drop-based fault attacks on FPGAs using valid bitstreams

DRE Gnad, F Oboril, MB Tahoori - 2017 27th International …, 2017 - ieeexplore.ieee.org
Due to the widespread use of FPGAs in many critical application domains, their security is of
high concern. In recent systems, such as FPGAs in the Cloud or in Systems-on-Chip (SoCs) …

Active fences against voltage-based side channels in multi-tenant FPGAs

J Krautter, DRE Gnad, F Schellenberg… - 2019 IEEE/ACM …, 2019 - ieeexplore.ieee.org
Dynamic and partial reconfiguration together with hardware parallelism make FPGAs
attractive as virtualized accelerators. However, recently it has been shown that multi-tenant …

Freely scalable and reconfigurable optical hardware for deep learning

L Bernstein, A Sludds, R Hamerly, V Sze, J Emer… - Scientific reports, 2021 - nature.com
As deep neural network (DNN) models grow ever-larger, they can achieve higher accuracy
and solve more complex problems. This trend has been enabled by an increase in available …

Noise-aware DVFS for efficient transitions on battery-powered IoT devices

C Zhuo, S Luo, H Gan, J Hu… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Low power system-on-chips (SoCs) are now at the heart of Internet-of-Things (IoT) devices,
which are well-known for their bursty workloads and limited energy storage-usually in the …

Safe limits on voltage reduction efficiency in GPUs: A direct measurement approach

J Leng, A Buyuktosunoglu, R Bertran, P Bose… - Proceedings of the 48th …, 2015 - dl.acm.org
Energy efficiency of GPU architectures has emerged as an important aspect of computer
system design. In this paper, we explore the energy benefits of reducing the GPU chip's …

Power management of datacenter workloads using per-core power gating

J Leverich, M Monchiero, V Talwar… - IEEE Computer …, 2009 - ieeexplore.ieee.org
While modern processors offer a wide spectrum of software-controlled power modes, most
datacenters only rely on Dynamic Voltage and Frequency Scaling (DVFS, aka P-states) to …

Power, thermal, and reliability modeling in nanometer-scale microprocessors

D Brooks, RP Dick, R Joseph, L Shang - Ieee Micro, 2007 - ieeexplore.ieee.org
System integration and performance requirements are dramatically increasing the power
consumptions and power densities of high-performance microprocessors. High power …

Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies

NH Khan, SM Alam, S Hassoun - IEEE Transactions on Very …, 2010 - ieeexplore.ieee.org
3-D integrated circuits promise high bandwidth, low latency, low device power, and a small
form factor. Increased device density and asymmetrical packaging, however, renders the …

Voltage emergency prediction: Using signatures to reduce operating margins

VJ Reddi, MS Gupta, G Holloway… - 2009 IEEE 15th …, 2009 - ieeexplore.ieee.org
Inductive noise forces microprocessor designers to sacrifice performance in order to ensure
correct and reliable operation of their designs. The possibility of wide fluctuations in supply …