With the down-scaling of CMOS technology, the design complexity of very large-scale
integrated is increasing. Although the application of machine learning (ML) techniques in …

Due to the increasing size of integrated circuits (ICs), their design and optimization phases
(ie, computer-aided design, CAD) grow increasingly complex. At design time, a large design …

The run-time for optimization tools used in chip design has grown with the complexity of
designs to the point where it can take several days to go through one design cycle which …

The efficient and timely optimization of microarchitecture for a target application is hindered
by the long evaluation runtime of a design candidate, creating a serious burden. To tackle …

The design automation community has been actively exploring machine learning (ML) for
very-large-scale-integrated (VLSI) computer-aided design (CAD). Many studies have …

Due to the rapid growth in the scale of circuits and the desire for knowledge transfer from old
designs to new ones, deep learning technologies have been widely exploited in Electronic …

It has been a long time that computer architecture and systems are optimized for efficient
execution of machine learning (ML) models. Now, it is time to reconsider the relationship …

Precise congestion prediction from a placement solution plays a crucial role in circuit
placement. This work proposes the lattice hypergraph (LH-graph), a novel graph formulation …

Placement and routing (PnR) is the most time-consuming part of the physical design flow.
Recognizing the routing performance ahead of time can assist designers and design tools to …

Congestion modeling is a key point for improving the routability of VLSI placement solutions.
The underuti-lization of netlist information limits the performance of ex-isting layout-based …