[PDF][PDF] Improved SNR and ENOB of Sigma-Delta Modulator for Post Simulation and High Level Modeling of Built-in-Self-Test Scheme

AK Sahu, VK Chandra, GR Sinha - International Journal of Computer …, 2014 - Citeseer
This paper demonstrates a Graphical User Interface (GUI) of 2nd order Sigma-Delta
modulator which is used to check the non-idealities of the circuit in BIST Scheme. High-level …

An Efficient Time-Tick based BIST Scheme to Calculate Static Errors of ADC

K Paldurai, K Hariharan - 2023 International Conference on …, 2023 - ieeexplore.ieee.org
BIST circuits have been increasingly used to test the data converters and evaluate the errors
in the same. A BIST scheme that completes the computation of the differential and integral …

A BIST scheme to test static parameters of ADCs

Z Hongyu, H Li - 2012 IEEE Symposium on Electrical & …, 2012 - ieeexplore.ieee.org
This paper presents a Built-in Self-Test (BIST) scheme for testing Analog-to-Digital
Converters (ADCs) static parameters, including Offset Error, Gain Error, Integral Non …

[PDF][PDF] A Cost Effective Built-in-Self Test for Second Order Sigma Delta Modulator

R Upadhyay, AK Sahu - International Journal of Computer Applications - Citeseer
Testing of high resolution second order sigma delta (ΣΔ) modulator is a very expensive
process. With the advanced technology, where the complexity over a small area is …

A simple testing structure for analog circuits

HW Ting - … Conference on Information Security and Intelligent …, 2012 - ieeexplore.ieee.org
This paper presents a simple current-mode testing structure for analog circuit. The proposed
structure is designed by the concept of the switch-current (SI) circuit. The proposed structure …

A Simple Capacitive Sensor with Digital-Compatibility Output

HW Ting, TT Hsieh, HY Wang - Sensor Letters, 2012 - ingentaconnect.com
This paper presents a simple current-mode interface circuit for capacitive sensing, with the
main features being its capability to produce a digital representation of the sensing output …

[ZITATION][C] DESIGN OF LINEAR RAMP GENERATOR AND DIGITAL ORA FOR AN AREA EFFICIENT HIGH SPEED ADC BIST