Review of 3D networks-on-chip simulators and plugins
A comprehensive review focuses on 3D network-on-chip (NoC) simulators and plugins while
paying attention to the 2D simulators as the baseline is presented. Discussions include the …
paying attention to the 2D simulators as the baseline is presented. Discussions include the …
Bandwidth-constrained multi-objective segmented brute-force algorithm for efficient map** of embedded applications on NoC architecture
Network-on-chip (NoC) is an emerging alternative to address the communication problem in
embedded system-on-chip designs. One of the key and major issues is the optimized …
embedded system-on-chip designs. One of the key and major issues is the optimized …
An efficient algorithm for map** real time embedded applications on NoC architecture
Network-on-chip (NoC) has appeared to be an impending substitute for the communication
paradigm in modern very large scale integration embedded systems. Apart from many …
paradigm in modern very large scale integration embedded systems. Apart from many …
NoC simulation steered by NEST: McAERsim and a Noxim patch
M Robens, R Kleijnen, M Schiek… - Frontiers in …, 2024 - frontiersin.org
Introduction Great knowledge was gained about the computational substrate of the brain, but
the way in which components and entities interact to perform information processing still …
the way in which components and entities interact to perform information processing still …
Comparative analysis of 2D mesh topologies with additional communication links for on-chip networks
Multiprocessor system-on-chip (MPSoC) is playing a vital role in recent embedded
technologies. One of the main challenges of this system is its communication bottleneck …
technologies. One of the main challenges of this system is its communication bottleneck …
Development of routing algorithms in networks-on-chip based on two-dimensional optimal circulant topologies
AY Romanov, EV Lezhnev, AY Glukhikh… - Heliyon, 2020 - cell.com
This work is devoted to the study of application of new topologies in the design of networks-
on-chip (NoCs). It is proposed to use two-dimensional optimal circulant topologies for NoC …
on-chip (NoCs). It is proposed to use two-dimensional optimal circulant topologies for NoC …
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster
Synchronization is likely the most critical performance killer in shared-memory parallel
programs. With the rise of multi-core and many-core processors, the relative impact on …
programs. With the rise of multi-core and many-core processors, the relative impact on …
Optical versus electrical: performance evaluation of network on-chip topologies for UWASN manycore processors
MR Yahya, N Wu, ZA Ali, Y Khizar - Wireless Personal Communications, 2021 - Springer
Optical network on chip (ONoC) has evolved as an innovative technology for on-chip
interconnects that can fulfill the upcoming requirements of manycore processors used in …
interconnects that can fulfill the upcoming requirements of manycore processors used in …
The octagonal-cross-by-pass-mesh topology design for the on-chip-communication
This article presents the novel Octagonal-Cross-By-Pass-Mesh (Octa-CBP-Mesh) network
topology design for on-chip communication. We have recently presented the cross-by-pass …
topology design for on-chip communication. We have recently presented the cross-by-pass …
An optimized hybrid algorithm in term of energy and performance for map** real time workloads on 2d based on-chip networks
In this paper, we propose an optimized, search based near-optimal map** heuristic,
named as ONMAP for map** real time embedded application workloads on 2D based on …
named as ONMAP for map** real time embedded application workloads on 2D based on …