CLEAR: Cache lines error accumulation reduction by exploiting invisible accesses

H Farbeh, AMH Monazzah - Microelectronics Journal, 2019 - Elsevier
SRAM caches are the most vulnerable processor component to radiation-induced soft
errors. Error-Correcting Codes (ECCs) are the conventional scheme to protect caches …

A 4× 4 8T-SRAM array with single-ended read and differential write scheme for low voltage applications

C Duari, S Birla, AK Singh - Semiconductor Science and …, 2021 - iopscience.iop.org
In ultra-low-power applications, the design of power-efficient static random access memory
(SRAM) is a major concern as it plays a significant part in leakage due to its higher density …

Protecting scratchpad memory addresses against soft errors

A Mansoor, M Fazeli, AM Rahmani - Microelectronics Reliability, 2020 - Elsevier
Scratchpad memories (SPMs) are intensively utilized in modern embedded processors
where a demand on improving reliability without compromising performance-predictability …

Early evaluation of multicore systems soft error reliability using virtual platforms

FR da Rosa, R Reis, L Ost - 2018 2nd Conference on PhD …, 2018 - ieeexplore.ieee.org
The increasing computing capacity of multicore components like processors and graphics
processing units (GPUs) offer new opportunities for embedded and high-performance …

A sub-threshold 9t sram cell with high write and read ability with bit interleaving capability

M Nobakht, R Niaraki - International Journal of Engineering, 2016 - ije.ir
This paper proposes a new sub-threshold low power 9T static random-access memory
(SRAM) cell compatible with bit interleaving structure in which the effective sizing adjustment …

Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability

FR Rosa, RM Brum, G Wirth, L Ost… - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
FinFET technology appears as an alternative solution to mitigate short-channel effects in
traditional CMOS down-scaled technology. Emerging embedded systems are likely to …

[BOOK][B] Soft Error Reliability Using Virtual Platforms: Early Evaluation of Multicore Systems

FR da Rosa, L Ost, R Reis - 2020 - books.google.com
This book describes the benefits and drawbacks inherent in the use of virtual platforms (VPs)
to perform fast and early soft error assessment of multicore systems. The authors show that …

Background on Soft Errors

F Rocha da Rosa, L Ost, R Reis… - Soft Error Reliability …, 2020 - Springer
Embedded systems reliability is a wide subject and complex subject. For this reason,
chapter two explores the main reliability challenges in electronic-based systems: Process …

[PDF][PDF] Hard IP Core Nondestructive Testing Technology

K Yu, H Wang - jommpublish.com
Based on the analysis of the existing hard IP core testing technology, the hard IP core
nondestructive testing technology was studied, according to the verification requirements of …

[PDF][PDF] Exploration of Reliability-oriented Design Techniques for Multicore Systems

FR da Rosa, L Ost, R Reis - academia.edu
The combination of constantly shrinking technology and ever-increasing on-chip power
density and temperature operation calls for novel reliability-oriented techniques which can …