Nanoscale resistive switching memory devices: a review

S Slesazeck, T Mikolajick - Nanotechnology, 2019 - iopscience.iop.org
In this review the different concepts of nanoscale resistive switching memory devices are
described and classified according to their I–V behaviour and the underlying physical …

Phase change memory technology

GW Burr, MJ Breitwisch, M Franceschini… - Journal of Vacuum …, 2010 - pubs.aip.org
The authors survey the current state of phase change memory (PCM), a nonvolatile solid-
state memory technology built around the large electrical contrast between the highly …

Overview of candidate device technologies for storage-class memory

GW Burr, BN Kurdi, JC Scott, CH Lam… - IBM Journal of …, 2008 - ieeexplore.ieee.org
Storage-class memory (SCM) combines the benefits of a solid-state memory, such as high
performance and robustness, with the archival capabilities and low cost of conventional hard …

Graphene flash memory

AJ Hong, EB Song, HS Yu, MJ Allen, J Kim, JD Fowler… - ACS …, 2011 - ACS Publications
Graphene's single atomic layer of sp2 carbon has recently garnered much attention for its
potential use in electronic applications. Here, we report a memory application for graphene …

Metal nanocrystal memories-part II: electrical characteristics

Z Liu, C Lee, V Narayanan, G Pei… - IEEE Transactions on …, 2002 - ieeexplore.ieee.org
This paper describes the electrical characteristics of the metal nanocrystal memory devices
continued from the previous paper [see ibid., vol. 49, p. 1606-13, Sept. 2002]. Devices with …

BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability

HT Lue, SY Wang, EK Lai, YH Shih… - … Meeting, 2005. IEDM …, 2005 - ieeexplore.ieee.org
A bandgap engineered SONOS with greatly improved reliability properties is proposed. This
concept is demonstrated by a multilayer structure of O1/N1/O2/N2/O3, where the ultra-thin" …

Operation scheme for programming charge trap** non-volatile memory

CI Wu - US Patent 7,190,614, 2007 - Google Patents
(57) ABSTRACT A circuit and method for self-converging programming of a charge storage
memory cell. Such as NROM or floating gate flash. The method includes determining a data …

Operation scheme for programming charge trap** non-volatile memory

CI Wu - US Patent 7,151,692, 2006 - Google Patents
A circuit and method for self-converging programming of a charge storage memory cell, such
as NROM or floating gate flash. The method includes determining a data value from one of …

Cause of data retention loss in a nitride-based localized trap** storage flash memory cell

WJ Tsai, SH Gu, NK Zous, CC Yeh… - … . 40th Annual (Cat …, 2002 - ieeexplore.ieee.org
Data retention loss in a localized trap** storage flash memory cell with a SONOS type
structure is investigated. Both charge loss through the bottom oxide and lateral migration of …

NROM memory cell, memory array, related devices and methods

KD Prall, L Forbes - US Patent 7,535,048, 2009 - Google Patents
US7535048B2 - NROM memory cell, memory array, related devices and methods - Google
Patents US7535048B2 - NROM memory cell, memory array, related devices and methods …