Replica bias circuit for high speed low voltage common mode driver

CQ Wu, YH Koh - US Patent 7,619,448, 2009 - Google Patents
A transmitter provides fast settling times, slew rate control, and power efficiency while
reducing the need for large external capacitors. The transmitter typically includes a pre …

A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission

G Ahn, DK Jeong, G Kim - IEEE Journal of Solid-State Circuits, 2000 - ieeexplore.ieee.org
A large-swing, voltage-mode driver and an on-chip termination circuit are presented for high-
speed nonreturn-to-zero (NRZ) data transmission through a copper cable. The proposed …

Low power low voltage differential signaling driver

M Chen, MA Nix - US Patent 6,927,608, 2005 - Google Patents
(57) ABSTRACT A low power LVDS driver includes a Switchable current module, a Source
termination circuit, a transistor Section, and a load current Source. The Switchable current …

1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-/spl mu/m CMOS

A Boni - IEEE Journal of Solid-State Circuits, 2001 - ieeexplore.ieee.org
This paper describes the design and the implementation of input-output (I/O) interface
circuits for serial data links in the gigabit-per-second range. The cells were implemented in a …

2.5 Gbps CMOS laser diode driver with APC and digitally controlled current modulation

CH Lin, IC Yao, CC Kuo, SJ Jou - Proceedings. IEEE Asia …, 2002 - ieeexplore.ieee.org
This laser diode driver operates at 2.5 Gbps. It contains a driver, a reference voltage
generator, an automatic power control circuit and digitally controlled blocks of bias current …

An overview of high-speed serial I/O trends, techniques and standards

F Zarkeshvari, P Noel, S Uhanov… - … on Electrical and …, 2004 - ieeexplore.ieee.org
The paper provides a brief overview of the basic building blocks within a high-speed serial
transceiver, provides an outline of the major interconnect standards utilizing the highspeed …

Low noise, reduced swing differential output buffer design

H Rai - US Patent 6,529,036, 2003 - Google Patents
The present invention concerns a circuit configured to match an impedance of a first pin and
a Second pin coupled to a transmission line. A first resistor is generally coupled to the first …

5 GHz PLL with current matching charge-pump for 10Gbps transmitter design

J Ko, W Lee, SW Kim - Proceedings of the 15th ACM Great Lakes …, 2005 - dl.acm.org
In this paper, we describe a mixed PLL architecture for low jitter clock generation that use a
proposed charge pump and output buffer. The newly designed charge-pump circuit is …

Voltage‐Mode 1.5 Gbps Interface Circuits for Chip‐to‐Chip Communication

KJ Lee, TH Kim, UR Cho, HG Byun, S Kim - ETRI journal, 2005 - Wiley Online Library
In this paper, interface circuits that are suitable for point‐to‐point interconnection with an
over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of …

High-speed serial I/O trends, standards and techniques

F Zarkeshvari, P Noel… - (ICEEE). 1st International …, 2004 - ieeexplore.ieee.org
The gad of this paper is to provide the reader with an overview of the major interconnect
standards utilizing the high-speed serial I/O circuitry and to outline several design …