With the down-scaling of CMOS technology, the design complexity of very large-scale
integrated is increasing. Although the application of machine learning (ML) techniques in …

Physical design process commonly consumes hours to days for large designs, and routing is
known as the most critical step. Demands for accurate routing quality prediction raise to a …

To speed up the FPGA placement and routing closure, we propose a novel approach to
predict the routing congestion map for large-scale FPGA designs at the placement stage …

Field-Programmable Gate Array (FPGA) is at the core of System on Chip (SoC) design
across various Industry 5.0 digital systems—healthcare devices, farming equipment …

As the scale of integrated circuits keeps increasing, it is witnessed that there is a surge in the
research of electronic design automation (EDA) to make the technology node scaling …

Avoiding congestion for routing resources has become one of the most important placement
objectives. In this paper, we present a machine-learning model for accurately and efficiently …

In the physical design of integrated circuits, global and detailed routing are critical stages
involving the determination of the interconnected paths of each net on a circuit while …

Placement and packing are two important but separated optimization steps in a conventional
field programmable gate array (FPGA) implementation flow. A packing engine clusters logic …

The ability to accurately and efficiently estimate the routability of a circuit based on its
placement is one of the most challenging and difficult tasks in the Field Programmable Gate …

elfPlace is a flat nonlinear placement algorithm for large-scale heterogeneous field-
programmable gate arrays (FPGAs). We adopt the analogy between placement and …