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MOSFET performance scaling—Part I: Historical trends
A Khakifirooz, DA Antoniadis - IEEE Transactions on Electron …, 2008 - ieeexplore.ieee.org
A simple analytical model that describes MOSFET operation in saturation from subthreshold
to strong inversion is used to derive a new formulation of the intrinsic switching delay of the …
to strong inversion is used to derive a new formulation of the intrinsic switching delay of the …
Strained CMOS device, circuit and method of fabrication
SW Bedell, K Cheng, BB Doris, A Khakifirooz… - US Patent …, 2012 - Google Patents
2. Description of the Related Art Strained silicon is being used by the semiconductor indus
try to improve transistor performance. Increased Strain levels are desired in future …
try to improve transistor performance. Increased Strain levels are desired in future …
On the variability in planar FDSOI technology: From MOSFETs to SRAM cells
In this paper, an in-depth variability analysis, ie, from the threshold voltage VT of metal-oxide-
semiconductor field-effect-transistors (MOSFETs) to the static noise margin (SNM) of static …
semiconductor field-effect-transistors (MOSFETs) to the static noise margin (SNM) of static …
Negative bias temperature instability (NBTI) recovery with bake
AA Katsetos - Microelectronics Reliability, 2008 - Elsevier
Negative bias temperature instability (NBTI) is a major degradation mechanism of PMOSFET
devices. When the p-channel field effect transistor (PFET) gate is biased negatively with …
devices. When the p-channel field effect transistor (PFET) gate is biased negatively with …
Performance enhancement in uniaxial strained silicon-on-insulator N-MOSFETs featuring silicon–carbon source/drain regions
KW Ang, KJ Chui, CH Tung… - IEEE transactions on …, 2007 - ieeexplore.ieee.org
We report the demonstration of a novel strained silicon-on-insulator N-MOSFET featuring
silicon-carbon (Si 1-y C y) source and drain (S/D) regions, tantalum nitride metal gate, and …
silicon-carbon (Si 1-y C y) source and drain (S/D) regions, tantalum nitride metal gate, and …
Transport enhancement techniques for nanoscale MOSFETs
A Khakifirooz - 2008 - dspace.mit.edu
(cont) While III-V semiconductors are seriously limited by their small quantization effective
mass, which limits the available inversion charge at a given voltage overdrive, germanium is …
mass, which limits the available inversion charge at a given voltage overdrive, germanium is …
Device structure, layout and fabrication method for uniaxially strained transistors
SW Bedell, H Bu, K Cheng, BB Doris… - US Patent …, 2012 - Google Patents
2. Description of the Related Art Epitaxially grown SiGe channels are being used to tune
threshold voltages of p-type metal oxide semiconductor field effect transistors (PMOSFETs) …
threshold voltages of p-type metal oxide semiconductor field effect transistors (PMOSFETs) …
Modélisation du transport sous contrainte mécanique dans les transistors sub-65 nm pour la microélectronique CMOS
K Huet - 2008 - theses.hal.science
La course à la miniaturisation des transistors MOS (Métal Oxyde Semiconducteur) implique
l'utilisation de nouvelles technologies d'amélioration des performances. Notamment …
l'utilisation de nouvelles technologies d'amélioration des performances. Notamment …
[PDF][PDF] Etude des effets des contraintes mécaniques induites par les procédés de fabrication sur le comportement électrique des transistors CMOS des nœuds …
C Ortolland - 2006 - researchgate.net
Le travail d'une thèse n'est pas quelque chose qui peut se faire seul et isolé des autres.
Comme toute étude de cette envergure, sa réussite est avant tout la réussite d'un groupe et …
Comme toute étude de cette envergure, sa réussite est avant tout la réussite d'un groupe et …
Device structure, layout and fabrication method for uniaxially strained transistors
SW Bedell, H Bu, K Cheng, BB Doris… - US Patent …, 2015 - Google Patents
(57) ABSTRACT A semiconductor device and method for fabricating a semi conductor
device include providing a strained semiconductor layer having a first strained axis, forming …
device include providing a strained semiconductor layer having a first strained axis, forming …