Dynamic power-gating for leakage power reduction in FPGAs
H Jahanirad - Frontiers of Information Technology & Electronic …, 2023 - Springer
Field programmable gate array (FPGA) devices have become widespread in electronic
systems due to their low design costs and reconfigurability. In battery-restricted applications …
systems due to their low design costs and reconfigurability. In battery-restricted applications …
Faster-than-real-time hardware emulation of transients and dynamics of a grid of microgrids
Enhanced environmental standards are leading to an increasing proportion of microgrids
(MGs) being integrated with renewable energy resources in modern power systems, which …
(MGs) being integrated with renewable energy resources in modern power systems, which …
Noise constrained optimum selection of supply voltage for IoT applications
An optimization technique is proposed to set the supply voltage of an integrated circuit for a
given range of threshold voltages. The algorithm accounts for the variations in maximum …
given range of threshold voltages. The algorithm accounts for the variations in maximum …
[書籍][B] Power Management Techniques for Ultra-Low Voltage Integrated Circuits
MS Hossain - 2021 - search.proquest.com
Energy efficient computing is one of the primary requirements of ubiquitous battery-operated
edge devices including mobile phones, wearables, active implantable medical devices …
edge devices including mobile phones, wearables, active implantable medical devices …
Low-power loop pipelining map** onto CGRA utilizing variable dual VDD
Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform based on its
high-performance and low cost. Researchers have developed efficient compilers for …
high-performance and low cost. Researchers have developed efficient compilers for …
Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD
Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform based on its
high-performance and low cost. Researchers have developed efficient compilers for …
high-performance and low cost. Researchers have developed efficient compilers for …
A concise and precise model of the gate delay for EDA simulation
Z Yue, Z Huang, D Chen, T Su - 2017 China Semiconductor …, 2017 - ieeexplore.ieee.org
This paper considers the relationship between the static gate delay and the supply voltage
of the digital integrated circuit. An empirical equation with physical implication is proposed …
of the digital integrated circuit. An empirical equation with physical implication is proposed …
Adaptation of counters redundant bits with the provision of dual supply and modified clock gating to favour of low power in VLS
M Sulaiman, A Bennet - Indian Journal of Pure & Applied Physics …, 2020 - op.niscpr.res.in
The utilization of usual supply voltage and clock for repetitive state transistors in digital
circuits is a fundamental driver for high power utilization. Most significant bit states of the …
circuits is a fundamental driver for high power utilization. Most significant bit states of the …