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3D floorplanning using 2D and 3D blocks
The disclosed embodiments are directed to systems and method for floorplanning an
integrated circuit design using a mix of 2D and 3D blocks that provide a significant improve …
integrated circuit design using a mix of 2D and 3D blocks that provide a significant improve …
Monolithic three dimensional integration of semiconductor integrated circuits
Y Du - US Patent 9,177,890, 2015 - Google Patents
(57) ABSTRACT A three-dimensional integrated circuit comprising top tier nanowire
transistors formed on a bottom tier of CMOS tran sistors, with inter-tier vias, intra-tier vias …
transistors formed on a bottom tier of CMOS tran sistors, with inter-tier vias, intra-tier vias …
Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods
Y Du - US Patent 9,536,840, 2017 - Google Patents
(57) ABSTRACT A three-dimensional (3-D) integrated circuit (3DIC) with a graphene shield
is disclosed. In certain embodiments, at least a graphene layer is positioned between two …
is disclosed. In certain embodiments, at least a graphene layer is positioned between two …
Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related methods
Y Du, J **e, K Samadi - US Patent 9,041,448, 2015 - Google Patents
PLLC (65) Prior Publication Data(57) ABSTRACT US 2014/O253196A1 Sep. 11, 2014 Flip-
flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method …
flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method …
Data transfer across power domains
J **e, Y Du - US Patent 8,984,463, 2015 - Google Patents
The disclosed embodiments comprise a multi-stage circuit operating across different power
domains. The multi-stage circuit may be implemented as a master-slave? ip-? op circuit …
domains. The multi-stage circuit may be implemented as a master-slave? ip-? op circuit …
Clock distribution network for 3D integrated circuit
5,724,557 A* 3/1998 McBean, Sr.................. T16, 113 2011/O121366 A1 5/2011 Or-Bach et
al. 6,040,203 A 3/2000 Bozso et al. 2011/0215300 A1 9, 2011 Guo et al. 6,125,217 A 9 …
al. 6,040,203 A 3/2000 Bozso et al. 2011/0215300 A1 9, 2011 Guo et al. 6,125,217 A 9 …
Superstrate sub-cell voltage-matched multijunction solar cells
A Mascarenhas, K Alberi - US Patent 9,287,431, 2016 - Google Patents
Voltage-matched thin film multijunction solar cell and meth ods of producing cells having
upper CdTe pnjunction layers formed on a transparent Substrate which in the completed …
upper CdTe pnjunction layers formed on a transparent Substrate which in the completed …
Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods
J **e, Y Du - US Patent 9,171,608, 2015 - Google Patents
(57) ABSTRACT A three-dimensional (3D) memory cell separation among 3D integrated
circuit (IC)(3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are …
circuit (IC)(3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are …
Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICs), 3DIC processor cores, and methods
J **e, Y Du - US Patent 9,583,179, 2017 - Google Patents
US9583179B2 - Three-dimensional (3D) memory cell separation among 3D integrated
circuit (IC) tiers, and related 3D integrated circuits (3DICs), 3DIC processor cores, and …
circuit (IC) tiers, and related 3D integrated circuits (3DICs), 3DIC processor cores, and …
Method for producing structured microcarriers
The present invention relates to a method for producing microcarriers, the method
comprising the steps of providing a wafer having a bottom layer, a top layer and an …
comprising the steps of providing a wafer having a bottom layer, a top layer and an …