Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple
processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) …

On-chip interconnection networks for future systems on chip (SoC) will have to deal with the
increasing sensitivity of global wires to noise sources such as crosstalk or power supply …

In this paper, we present a coding framework derived from a communication-theoretic view
of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is …

We present techniques to analyze and alleviate cross-talk in on-chip buses. With rapidly
shrinking process feature sizes, wire delay is becoming a large fraction of the overall delay …

Interconnect delay has become a limiting factor for circuit performance in deep sub-
micrometer designs. As the crosstalk in an on-chip bus is highly dependent on the data …

The coupling capacitances between on-chip bus lines become dominant in deep-submicron
technologies. Coding to reduce the switching activity of the individual lines was enough to …

An ever more significant fraction of the overall power dissipation of a network-on-chip (NoC)
based system-on-chip (SoC) is due to the interconnection system. In fact, as technology …

As technology shrinks, the power dissipated by the links of a network-on-chip (NoC) starts to
compete with the power dissipated by the other elements of the communication subsystem …

We propose a novel approach to bus energy minimization that targets crosstalk effects.
Unlike previous approaches, we try to reduce energy through capacitance optimization, by …