Advances in logic locking: Past, present, and prospects

HM Kamali, KZ Azar, F Farahmandi… - Cryptology ePrint …, 2022 - eprint.iacr.org
Logic locking is a design concealment mechanism for protecting the IPs integrated into
modern System-on-Chip (SoC) architectures from a wide range of hardware security threats …

Protect your chip design intellectual property: An overview

J Knechtel, S Patnaik, O Sinanoglu - Proceedings of the International …, 2019 - dl.acm.org
The increasing cost of integrated circuit (IC) fabrication has driven most companies to" go
fabless" over time. The corresponding outsourcing trend gave rise to various attack vectors …

A survey on split manufacturing: Attacks, defenses, and challenges

TD Perez, S Pagliarini - IEEE Access, 2020 - ieeexplore.ieee.org
In today's integrated circuit (IC) ecosystem, owning a foundry is not economically viable, and
therefore most IC design houses are now working under a fabless business model. In order …

Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging

S Patnaik, M Ashraf, O Sinanoglu… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Layout camouflaging can protect the intellectual property of modern circuits. Most prior art,
however, incurs excessive layout overheads and necessitates customization of active …

Towards secure composition of integrated circuits and electronic systems: On the role of EDA

J Knechtel, EB Kavun, F Regazzoni… - … , Automation & Test …, 2020 - ieeexplore.ieee.org
Modern electronic systems become evermore complex, yet remain modular, with integrated
circuits (ICs) acting as versatile hardware components at their heart. Electronic design …

Hardware security for and beyond CMOS technology: an overview on fundamentals, applications, and challenges

J Knechtel - Proceedings of the 2020 International Symposium on …, 2020 - dl.acm.org
As with most aspects of electronic systems and integrated circuits, hardware security has
traditionally evolved around the dominant CMOS technology. However, with the rise of …

Concerted wire lifting: Enabling secure and cost-effective split manufacturing

S Patnaik, M Ashraf, H Li, J Knechtel… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
In this work, we advance the security promise of split manufacturing through judicious
handling of interconnects. First, we study the cost-security tradeoffs underlying for split …

Hardware security for and beyond CMOS technology

J Knechtel - Proceedings of the 2021 International Symposium on …, 2021 - dl.acm.org
As with most aspects of electronic systems and integrated circuits, hardware security has
traditionally evolved around the dominant CMOS technology. However, with the rise of …

Raise your game for split manufacturing: Restoring the true functionality through BEOL

S Patnaik, M Ashraf, J Knechtel… - Proceedings of the 55th …, 2018 - dl.acm.org
Split manufacturing (SM) seeks to protect against piracy of intellectual property (IP) in chip
designs. Here we propose a scheme to manipulate both placement and routing in an …

Analysis of security of split manufacturing using machine learning

B Zhang, JC Magaña, A Davoodi - Proceedings of the 55th Annual …, 2018 - dl.acm.org
This work is the first to analyze the security of split manufacturing using machine learning,
based on data collected from layouts provided by industry, with 8 routing metal layers, and …