Apparatus and method of compressing neural network

OH Youngmin - US Patent 12,124,957, 2024 - Google Patents
Provided are an apparatus and method of compressing an artificial neural network.
According to the method and the apparatus, an optimal compression rate and an optimal …

Question and answer pair generation using machine learning

P Bajaj, G Boland, A Gupta, MG **… - US Patent …, 2022 - Google Patents
An interactive question and answer (Q & A) service provides pairs of questions and
corresponding answers related to the content of a web page. The service includes pre …

Dot product operations on sparse matrix elements

A Appu, S Maiyuran, M MacPherson, F Fu… - US Patent …, 2023 - Google Patents
2020-12-16 Assigned to INTEL CORPORATION reassignment INTEL CORPORATION
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

S Maiyuran, S Marwaha, A Garg, S Pal, J Parra… - US Patent …, 2022 - Google Patents
Described herein is a graphics processing unit (GPU) com prising a single instruction,
multiple thread (SIMT) multi processor comprising an instruction cache, a shared memory …

Systolic arithmetic on sparse data

AR Appu, P Surti, J Boyce, S Maiyuran… - US Patent …, 2023 - Google Patents
2021-03-04 Assigned to INTEL CORPORATION reassignment INTEL CORPORATION
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …

Graphics processor operation scheduling for deterministic latency

J Ray, S Panneer, S Tangri, B Ashbaugh… - US Patent …, 2024 - Google Patents
Embodiments described herein include software, firmware, and hardware that provides
techniques to enable deterministic scheduling across multiple general-purpose graphics …

Instructions and logic to perform floating point and integer operations for machine learning

H Kaul, MA Anders, SK Mathew, A Yao, J Ray… - US Patent …, 2022 - Google Patents
(57) ABSTRACT A processing apparatus is provided comprising a multipro cessor having a
multithreaded architecture. The multipro cessor can execute at least one single instruction to …

Instruction based control of memory attributes

J Ray, A Koker, V George, M MacPherson… - US Patent …, 2024 - Google Patents
Embodiments described herein provide techniques to facilitate instruction-based control of
memory attributes. One embodiment provides a graphics processor comprising a processing …

Pruning redundant neurons and kernels of deep convolutional neural networks

CF Chen, JH Lai, CY Lin, YE Guangnan… - US Patent …, 2021 - Google Patents
US11093832B2 - Pruning redundant neurons and kernels of deep convolutional neural networks
- Google Patents US11093832B2 - Pruning redundant neurons and kernels of deep convolutional …

Sparse optimizations for a matrix accelerator architecture

J Ray, S Janus, V George, S Maiyuran… - US Patent …, 2023 - Google Patents
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C (= O) N [C@ H](C [C@ H](O)[C@ H](CC= 2C= CC= CC= 2) NC (= O) COC= 2C (= CC …