A high-throughput memory-efficient decoder architecture for low-density parity-check
(LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture …

Sage passing decoding techniques which are particularly well suited for use with low
density parity check (LDPC) codes and long codewords are described. The described …

A 14.3-mm/sup 2/code-programmable and code-rate tunable decoder chip for 2048-bit low-
density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding …

613371642 B1 V2002 Yaoilleta' 2003/0081693 A1 5/2003 Raghaven etal. 1 1 g.
2003/0087634 A1 5/2003 Raghaven et a1. 613511832 B1 2/2002 We ' 2003/0112896 A1 …

US8418023B2 - Low density parity check decoder for irregular LDPC codes - Google Patents
US8418023B2 - Low density parity check decoder for irregular LDPC codes - Google Patents …

This paper presents a semi-parallel architecture for decoding low density parity check
(LDPC) codes. A modified version of min-sum algorithm has been used which the …

7.313, 752 B2 12/2007 Kyung et al. intermediate Sub-vector based on a permutation
coefficient 7,607,075 B2 10/2009 Blankenship et al. corresponding to another block in the …

(57) ABSTRACT A flexible and relatively hardware efficient LDPC encoder is described. The
encoder can be implemented with a level of parallelism which is less than the full parallelism …

Methods and apparatus for encoding codewords which are particularly well Suited for use
with low density parity check (LDPC) codes and long codewords are described. The …

Many classes of high-performance low-density parity-check (LDPC) codes are based on
parity check matrices composed of permutation submatrices. We describe the design of a …