Networks-on-Chip constitute the interconnection architecture of future, massively parallel
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …

Increasing fault rates in current and future technology nodes coupled with on-chip
components in the hundreds calls for robust and fault-tolerant Network-on-Chip (NoC) …

In this paper, we propose a distributed routing algorithm for vertically partially connected
regular 2D topologies of different shapes and sizes (eg, 2D mesh, torus, ring). The …

The widespread proliferation of the Chip Multi-Processor (CMP) paradigm has cemented the
criticality of the on-chip interconnection fabric. The Network-on-Chip (NoC) is becoming …

Aggressive transistor scaling continues to drive increasingly complex digital designs. The
large number of transistors available today enables the development of chip multiprocessors …

Most standard cluster interconnect technologies are flexible with respect to network
topology. This has spawned a substantial amount of research on topology-agnostic routing …

Applications' traffic tends to be bursty and the location of hot-spot nodes moves as time goes
by. This will significantly aggregate the blocking problem of wormhole-routed Network-on …

Abstract Three-Dimensional Networks-on-Chip (3D-NoC) has been presented as an
auspicious solution merging the high parallelism of Network-on-Chip (NoC) interconnect …

In this work, we propose a distributed functional test mechanism for NoCs which scales to
large-scale networks with general topologies and routing algorithms. Each router and its …

Fault tolerance and adaptive capabilities are challenges for modern networks-on-chip (NoC)
due to the increase in physical defects in advanced manufacturing processes. Two novel …