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Aging mitigation in memory arrays using self-controlled bit-flip** technique
With CMOS technology downscaling into the nanometer regime, the reliability of SRAM
memories is threatened by accelerated transistor aging mechanisms such as Bias …
memories is threatened by accelerated transistor aging mechanisms such as Bias …
Aging benefits in nanometer CMOS designs
In this brief, we show that bias temperature instability (BTI) aging of MOS transistors,
together with its detrimental effect for circuit performance and lifetime, presents considerable …
together with its detrimental effect for circuit performance and lifetime, presents considerable …
Impact of bias temperature instability on soft error susceptibility
In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft
error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely …
error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely …
CASSER: A closed-form analysis framework for statistical soft error rate
ACC Chang, RHM Huang… - IEEE Transactions on Very …, 2012 - ieeexplore.ieee.org
CMOS designs in the deep submicrometer era require statistical methods to accurately
estimate the circuit soft error rate (SER). However, process variation increases the …
estimate the circuit soft error rate (SER). However, process variation increases the …
Reliable power gating with NBTI aging benefits
In this paper, we show that negative bias temperature instability (NBTI) aging of sleep
transistors (STs), together with its detrimental effect for circuit performance and lifetime (LT) …
transistors (STs), together with its detrimental effect for circuit performance and lifetime (LT) …
Design, use and evaluation of p-fsefi: A parallel soft error fault injection framework for emulating soft errors in parallel applications
Future exascale application programmers and users have a need to quantity an
application's resilience and vulnerability to soft errors before running their codes on …
application's resilience and vulnerability to soft errors before running their codes on …
A fault-tolerant design strategy utilizing approximate computing
This paper presents a novel Fault-tolerant design ie, redundancy strategy based on
Approximate Computing, which we call FAC. Conventionally, triple modular redundancy …
Approximate Computing, which we call FAC. Conventionally, triple modular redundancy …
Analysis of Redundancy Techniques for Electronics Design—Case Study of Digital Image Processing
Electronic circuits/systems operating in harsh environments such as space are likely to
experience faults or failures due to the impact of high-energy radiation. Given this, to …
experience faults or failures due to the impact of high-energy radiation. Given this, to …
Soft error rate estimation of combinational circuits based on vulnerability analysis
Nanometer integrated circuits are getting increasingly vulnerable to soft errors and making
the soft error rate (SER) estimation an important challenge. In this study, a novel approach is …
the soft error rate (SER) estimation an important challenge. In this study, a novel approach is …
Impact of aging phenomena on latches' robustness
In this paper, we analyze the effects of aging mechanisms on the soft error susceptibility of
both standard and robust latches. Particularly, we consider bias temperature instability (BTI) …
both standard and robust latches. Particularly, we consider bias temperature instability (BTI) …