From verification to causality-based explications

C Baier, C Dubslaff, F Funke, S Jantsch… - arxiv preprint arxiv …, 2021 - arxiv.org
In view of the growing complexity of modern software architectures, formal models are
increasingly used to understand why a system works the way it does, opposed to simply …

[KIRJA][B] Advanced formal verification

R Drechsler - 2004 - Springer
Modern circuits may contain up to several hundred million transistors. In the meantime it has
been observed that verification becomes the major bottleneck in design flows, ie up to 80 …

Coverage metrics for requirements-based testing

MW Whalen, A Rajan, MPE Heimdahl… - Proceedings of the 2006 …, 2006 - dl.acm.org
In black-box testing, one is interested in creating a suite of tests from requirements that
adequately exercise the behavior of a software system without regard to the internal …

Specification: The biggest bottleneck in formal methods and autonomy

KY Rozier - Working Conference on Verified Software: Theories …, 2016 - Springer
Advancement of AI-enhanced control in autonomous systems stands on the shoulders of
formal methods, which make possible the rigorous safety analysis autonomous systems …

Mining hardware assertions with guidance from static analysis

S Hertz, D Sheridan… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
We present GoldMine, a methodology for generating assertions automatically in hardware.
Our method involves a combination of data mining and static analysis of the register transfer …

What causes a system to satisfy a specification?

H Chockler, JY Halpern, O Kupferman - ACM Transactions on …, 2008 - dl.acm.org
Even when a system is proven to be correct with respect to a specification, there is still a
question of how complete the specification is, and whether it really covers all the behaviors …

[KIRJA][B] Equivalence checking of digital circuits: fundamentals, principles, methods

P Molitor, J Mohnke - 2004 - books.google.com
Hardware verification is the process of checking whether a design conforms to its
specification of functionality. In today's design processes it becomes more and more …

Coverage metrics for formal verification

H Chockler, O Kupferman, MY Vardi - … 2003, L'Aquila, Italy, October 21-24 …, 2003 - Springer
In formal verification, we verify that a system is correct with respect to a specification. Even
when the system is proven to be correct, there is still a question of how complete the …

Safety and software intensive systems: Challenges old and new

MPE Heimdahl - Future of Software Engineering (FOSE'07), 2007 - ieeexplore.ieee.org
There is an increased use of software in safety-critical systems; a trend that is likely to
continue in the future. Although traditional system safety techniques are applicable to …

Sanity checks in formal verification

O Kupferman - International Conference on Concurrency Theory, 2006 - Springer
One of the advantages of temporal-logic model-checking tools is their ability to accompany a
negative answer to the correctness query by a counterexample to the satisfaction of the …