Benefits of DfX in requirements engineering

J Lehto, J Harkonen, H Haapasalo, P Belt… - Technology and …, 2011‏ - scirp.org
Information and communications technology (ICT) companies have realised how
acknowledging the needs of both internal and external customers is a necessity for …

Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits

C Sebeke, JP Teixeira, MJ Ohletz - Proceedings the European …, 1995‏ - ieeexplore.ieee.org
A comprehensive tool has been implemented for the comparison of different test preparation
techniques and target faults. It comprises of the realistic fault characterisation program LIFT …

Dynamic segment intersection search with applications

H Imai, T Asano - 25th Annual Symposium onFoundations of …, 1984‏ - ieeexplore.ieee.org
In this paper, we consider two restricted types of dynamic orthogonal segment intersection
search problems. One is the problem in which the underlying set is updated only by …

Realistic faults map** scheme for the fault simulation of integrated analogue CMOS circuits

MJ Ohletz - … International Test Conference 1996. Test and …, 1996‏ - ieeexplore.ieee.org
A new fault modelling scheme for integrated analogue CMOS circuits referred to as Local
Layout Realistic Fault Map** is introduced. It is aimed at realistic fault assumptions prior to …

IC defects-based testability analysis

JT Sousa, FM Gonçalves, JP Teixeira - Proceedings of the IEEE …, 1991‏ - dl.acm.org
IC Defects-Based Testability Analysis | Proceedings of the IEEE International Test Conference
on Test: Faster, Better, Sooner skip to main content ACM Digital Library home ACM Association …

CMOS IC fault models, physical defect coverage, and I/sub DDQ/testing

RR Fritzemeier, CF Hawkins… - Proceedings of the IEEE …, 1991‏ - ieeexplore.ieee.org
The development of the stuck-at fault (SAF) model is reviewed with emphasis on its
relationship to CMOS integrated circuit (IC) technologies. The ability of the SAF model to …

Highly testable and compact single output comparator

C Metra, M Favalli, B Riccò - Proceedings. 15th IEEE VLSI Test …, 1997‏ - ieeexplore.ieee.org
In this paper a single output self-checking n-input comparator is presented. The proposed
circuit, which can be used as n-variable two-rail checker or as equality checker features a …

On-line testing scheme for clock's faults

C Metra, M Favalli, B Ricco - Proceedings International Test …, 1997‏ - ieeexplore.ieee.org
This paper proposes an on-line testing scheme for permanent and temporary faults which
affect signals of the clock distribution network of synchronous systems, and which make …

[PDF][PDF] Physical DFT for High Coverage of Realistic Faults.

M Saraiva, P Casimiro, MB Santos, JT de Sousa… - ITC, 1992‏ - researchgate.net
Test quality requires the ability of test patterns to cover realistic faults originated by physical
defects induced during IC manufacturing. Recent progress in a methodology for physical …

New efficient totally self-checking Berger code checkers

X Kavousianos, D Nikolos, G Foukarakis, T Gnardellis - Integration, 1999‏ - Elsevier
This paper presents a new method for designing totally self-checking (TSC) Berger code
checkers for any number k of information bits, even for k= 2r− 1, taking into account realistic …