NASCENT: Near-storage acceleration of database sort on SmartSSD
As the size of data generated every day grows dramatically, the computational bottleneck of
computer systems has been shifted toward the storage devices. Thanks to recent …
computer systems has been shifted toward the storage devices. Thanks to recent …
High-level synthesis hardware design for fpga-based accelerators: Models, methodologies, and frameworks
Hardware accelerators based on field programmable gate array (FPGA) and system on chip
(SoC) devices have gained attention in recent years. One of the main reasons is that these …
(SoC) devices have gained attention in recent years. One of the main reasons is that these …
An experimental study of reduced-voltage operation in modern FPGAs for neural network acceleration
We empirically evaluate an undervolting technique, ie, underscaling the circuit supply
voltage below the nominal level, to improve the power-efficiency of Convolutional Neural …
voltage below the nominal level, to improve the power-efficiency of Convolutional Neural …
Accelerating hyperdimensional computing on fpgas by exploiting computational reuse
Brain-inspired hyperdimensional (HD) computing emulates cognition by computing with
long-size vectors. HD computing consists of two main modules: encoder and associative …
long-size vectors. HD computing consists of two main modules: encoder and associative …
A survey of FPGA optimization methods for data center energy efficiency
M Tibaldi, C Pilato - IEEE Transactions on Sustainable …, 2023 - ieeexplore.ieee.org
This article provides a survey of academic literature about field programmable gate array
(FPGA) and their utilization for energy efficiency acceleration in data centers. The goal is to …
(FPGA) and their utilization for energy efficiency acceleration in data centers. The goal is to …
FODM: A framework for accurate online delay measurement supporting all timing paths in FPGA
Voltage and frequency scaling (VFS) has been widely used to improve energy efficiency,
lifespan, and system reliability by converting conservative timing margins into reduction …
lifespan, and system reliability by converting conservative timing margins into reduction …
ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors
S Ji, W Yang, J Jiang, N **g, W Sheng… - 2023 IEEE 41st …, 2023 - ieeexplore.ieee.org
To ensure the correctness and reliability, digital circuits are designed with conservative
timing margins to accommodate extreme variations in process, voltage, and temperature …
timing margins to accommodate extreme variations in process, voltage, and temperature …
A machine learning pipeline stage for adaptive frequency adjustment
AF Ajirlou, I Partin-Vaisband - IEEE Transactions on Computers, 2021 - ieeexplore.ieee.org
A machine learning (ML) design framework is proposed for adaptively adjusting clock
frequency based on propagation delay of individual instructions. A random forest model is …
frequency based on propagation delay of individual instructions. A random forest model is …
MACS: A Multi-Domain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators
S Ji, W Yang, J Jiang, N **g, H Jiang… - … on Computer-Aided …, 2025 - ieeexplore.ieee.org
To guarantee reliability and correctness, VLSI circuits are designed with conservative
margins to maintain timing and power integrity against process, voltage, and temperature …
margins to maintain timing and power integrity against process, voltage, and temperature …
Design of thermal-aware and power-efficient LFSR on different nanometer technology FPGA for green communication
With the advancement in technologies, industrialization, and rapid growth of population, the
globe is much affected by the mess of power and energy crisis. Therefore, there is a need for …
globe is much affected by the mess of power and energy crisis. Therefore, there is a need for …