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Selective hardening: Toward cost-effective error tolerance
As ICs shrink into the nanometer range, they are increasingly subject to errors induced by
physical faults. Traditional hardening for error mitigation consumes too much area and …
physical faults. Traditional hardening for error mitigation consumes too much area and …
Combined DVFS and map** exploration for lifetime and soft-error susceptibility improvement in MPSoCs
Energy and reliability optimization are two of the most critical objectives for the synthesis of
multiprocessor systems-on-chip (MPSoCs). Task map** has shown significant promise as …
multiprocessor systems-on-chip (MPSoCs). Task map** has shown significant promise as …
Reliability-driven system-level synthesis for mixed-critical embedded systems
This paper proposes a design methodology that enhances the classical system-level design
flow for embedded systems to introduce reliability-awareness. The map** and scheduling …
flow for embedded systems to introduce reliability-awareness. The map** and scheduling …
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
Reliability is a major requirement for most safety-related systems. To meet this requirement,
fault-tolerant techniques such as hardware replication and software re-execution are often …
fault-tolerant techniques such as hardware replication and software re-execution are often …
Leveraging weakly-hard constraints for improving system fault tolerance with functional and timing guarantees
Many safety-critical real-time systems operate under harsh environment and are subject to
soft errors caused by transient or intermittent faults. It is critical and yet often very challenging …
soft errors caused by transient or intermittent faults. It is critical and yet often very challenging …
Aging-aware hardware-software task partitioning for reliable reconfigurable multiprocessor systems
Homogeneous multiprocessor systems with reconfigurable area (also known as
Reconfigurable Multiprocessor Systems) are emerging as a popular design choice in current …
Reconfigurable Multiprocessor Systems) are emerging as a popular design choice in current …
Analysis and optimization of soft error tolerance strategies for real-time systems
The safety of real-time embedded systems relies on both functional and timing correctness.
On the timing side, realtime constraints are set on task executions, and missing them may …
On the timing side, realtime constraints are set on task executions, and missing them may …
Toward efficient design space exploration for fault-tolerant multiprocessor systems
The design space exploration (DSE) of fault-tolerant multiprocessor systems is very
complex, as it contains three interacting NP-hard problems: 1) task hardening; 2) task …
complex, as it contains three interacting NP-hard problems: 1) task hardening; 2) task …
Reliable code generation and execution on unreliable hardware under joint functional and timing reliability considerations
To enable reliable embedded systems, it is imperative to leverage the compiler and system
software for joint optimization of functional correctness, ie, vulnerability indexes, and timing …
software for joint optimization of functional correctness, ie, vulnerability indexes, and timing …
CL (R) early: An early-stage DSE methodology for cross-layer reliability-aware heterogeneous embedded systems
Cross-layer reliability (CLR) presents a cost-effective alternative to traditional single-layer
design in resource-constrained embedded systems. CLR provides the scope for leveraging …
design in resource-constrained embedded systems. CLR provides the scope for leveraging …