Networks-on-Chip constitute the interconnection architecture of future, massively parallel
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …

Wormhole routing has emerged as the most widely used switching technique in massively
parallel computers. We present a detailed survey of various techniques for enhancing the …

The performance of most digital systems today is limited by their communication or
interconnection, not by their logic or memory. As designers strive to make more efficient use …

Current trends in technology scaling foreshadow worsening transistor reliability as well as
greater numbers of transistors in each system. The combination of these factors will soon …

In this paper we present a reconfigurable routing algorithm for a 2D-Mesh Network-on-Chip
(NoC) dedicated to fault-tolerant, Massively Parallel Multi-Processors Systems on Chip (MP2 …

Future requirements for computing speed, system reliability, and cost-effectiveness entail the
development of alternative computers to replace the traditional von Neumann organization …

We propose a deterministic fault-tolerant and deadlock-free routing protocol in two-
dimensional (2D) meshes based on dimension-order routing and the odd-even turn model …

In this paper, we propose a distributed routing algorithm for vertically partially connected
regular 2D topologies of different shapes and sizes (eg, 2D mesh, torus, ring). The …

In this paper, we present a novel fully adaptive and fault-tolerant routing algorithm for
Network-on-Chips (NoCs) called Force-Directed Wormhole Routing (FDWR). The proposed …

Due to limited functionalities and potentially large number of sensors, existing routing
strategies proposed for mobile ad hoc networks are not directly applicable to wireless …