Instruction level parallelism exploitation has become extremely costly in terms of power and
area, bringing insignificant performance gains, if one considers the last generation of …

As technology scaling reduces pace and energy efficiency becomes a new important design
constraint, superscalar processor designs are reaching their performance limits due to area …

As the number of embedded applications is increasing, the current strategy of several
companies is to launch a new platform within short periods, to execute the application set …

Modern embedded system must efficiently exploit parallelism at thread-and instruction-level
to achieve the best performance with the lowest energy consumption possible. While …

Over the past years, the growing performance gap between large memories and
computational logic fueled an increased usage of complex memory hierarchies. The main …

This work presents a hardware implementation of a on-thefly algorithm which performs three
tasks: scheduling, placement and routing for stream computing. The algorithm is a module …

Abstract Coarse Grained Reconfigurable Architectures (CGRA) have been widely used with
General Purpose Processors (GPP) to boost performance of applications by exploiting …

Even though reconfigurable systems have already proven to be an alternative to speedup
embedded applications with reduced energy costs, because of their adaptability and high …

As has been emphasized throughout this book, it is necessary a high level of adaptability to
cope with the high heterogeneous behavior of recent applications. At the same time, binary …

Um novo cenário emerge devido às nanotecnologias. Estas permitirão taxas de integração
elevadas, nos limites, ou mesmo além da capacidade atual do silício. Contudo, estimativas …