A 56-Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16-nm FinFET
A 56-Gb/s PAM4 wireline transceiver testchip is implemented in 16-nm FinFET. The current
mode logic transmitter incorporates an auxiliary current injection at the output nodes to …
mode logic transmitter incorporates an auxiliary current injection at the output nodes to …
Analog-to-digital converter-based serial links: An overview
The ever-increasing number of networked devices and cloud computing applications has
created dramatic growth in data center traffic. This necessitates that the serial links that …
created dramatic growth in data center traffic. This necessitates that the serial links that …
Performance, power, and area design trade-offs in millimeter-wave transmitter beamforming architectures
H Yan, S Ramesh, T Gallagher, C Ling… - IEEE Circuits and …, 2019 - ieeexplore.ieee.org
Millimeter wave (mmW) communications is viewed as the key enabler of 5G cellular
networks due to vast spectrum availability that could boost peak rate and capacity. Due to …
networks due to vast spectrum availability that could boost peak rate and capacity. Due to …
A reconfigurable 16/32 Gb/s dual-mode NRZ/PAM4 SerDes in 65-nm CMOS
While four-level pulse amplitude modulation (PAM4) standards are emerging to increase
bandwidth density, the majority of standards use simple binary non-returnto-zero (NRZ) …
bandwidth density, the majority of standards use simple binary non-returnto-zero (NRZ) …
A 64 Gb/s low-power transceiver for short-reach PAM-4 electrical links in 28-nm FDSOI CMOS
E Depaoli, H Zhang, M Mazzini… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
A four-level pulse-amplitude modulation (PAM-4) transceiver operating up to 64 Gb/s in 28-
nm CMOS fully depleted silicon-on-insulator (FDSOI) for short-reach electrical links is …
nm CMOS fully depleted silicon-on-insulator (FDSOI) for short-reach electrical links is …
A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC
K Yoshioka, H Kubota, T Fukushima… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
This paper presents a time-to-digital converter/analog-to-digital-converter (TDC/ADC) hybrid
LiDAR system-on-chip (SoC) to realize reliable self-driving systems. The smart accumulation …
LiDAR system-on-chip (SoC) to realize reliable self-driving systems. The smart accumulation …
A 56-GS/s 8-bit time-interleaved ADC with ENOB and BW enhancement techniques in 28-nm CMOS
K Sun, G Wang, Q Zhang… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
This paper presents a 31.5-GHz bandwidth (BW) 56-GS/s time-interleaved (TI) analog-to-
digital converter (ADC) with 5.7-b effective number of bits (ENOB) and 5.2-b ENOB up to …
digital converter (ADC) with 5.7-b effective number of bits (ENOB) and 5.2-b ENOB up to …
29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4× 64GS/s 8b ADCs and DACs in 20nm CMOS
At rates of 100Gb/s and above, CMOS DSP-based transceivers integrated with high-
sampling-rate data converters are critical to realize the phase-sensitive modulation schemes …
sampling-rate data converters are critical to realize the phase-sensitive modulation schemes …
Analysis and design of a foam-cladded PMF link with phase tuning in 28-nm CMOS
This paper presents a fully packaged 140-GHz dielectric waveguide (DWG) communication
link using a foam-cladded fiber. A novel frequency shift keying (FSK) demodulator topology …
link using a foam-cladded fiber. A novel frequency shift keying (FSK) demodulator topology …
A 115–135-GHz 8PSK receiver using multi-phase RF-correlation-based direct-demodulation method
This paper presents the theory, design, and implementation of an 8PSK direct-demodulation
receiver based on a novel multi-phase RF-correlation concept. The output of this RF-to-bits …
receiver based on a novel multi-phase RF-correlation concept. The output of this RF-to-bits …