Ferroelectric gating of two-dimensional semiconductors for the integration of steep-slope logic and neuromorphic devices

S Kamaei, X Liu, A Saeidi, Y Wei, C Gastaldi… - Nature …, 2023 - nature.com
The co-integration of logic switches and neuromorphic functions could be used to create
new computing architectures with low power consumption and novel functionalities. Two …

Physics based numerical model of a nanoscale dielectric modulated step graded germanium source biotube FET sensor: modelling and simulation

A Das, S Rewari, BK Kanaujia, SS Deswal… - Physica …, 2023 - iopscience.iop.org
This paper proposes a novel dielectric modulated step-graded germanium source biotube
FET for label-free biosensing applications. Its integrated structure and unique design …

Tunnel FET based SRAM cells–a comparative review

R Gadarapulla, S Sriadibhatla - … ICMDCS 2021, Vellore, India, February 11 …, 2021 - Springer
This paper reviews some of the recent developments in Tunnel FET based SRAM cells.
Tunnel Field Effect Transistor (TFET) is a potential contender to outperform CMOS at low …

TFET-based robust 7T SRAM cell for low power application

S Ahmad, SA Ahmad, M Muqeem… - IEEE transactions on …, 2019 - ieeexplore.ieee.org
TFETs have emerged as the potential candidate for future ultralow-power applications.
However, the unidirectionality and poor drive current are the biggest hurdles for their …

Impact of reverse gate oxide stacking on gate all around tunnel FET for high frequency analog and RF applications

A Das, BK Kanaujia, V Nath, S Rewari… - 2020 IEEE 17th India …, 2020 - ieeexplore.ieee.org
We have studied the impact of the reverse gate oxide stacking technique on a typical Gate
All Around Tunnel Field Effect Transistor (GAA TFET). For this, we have compared it's …

Impact of heterogeneous gate dielectric on DC, RF and circuit-level performance of source-pocket engineered Ge/Si heterojunction vertical TFET

MR Tripathy, AK Singh, A Samad… - Semiconductor …, 2020 - iopscience.iop.org
This paper reports the DC, RF and circuit-level performance analysis of short-channel Ge/Si
based source-pocket engineered (SPE) vertical heterojunction tunnel field effect transistors …

Design of 7T SRAM using InGaAs-dual pocket-dual gate-tunnel FET for IoT applications

G Rasheed, S Sridevi - IEEE Access, 2023 - ieeexplore.ieee.org
The Internet of Things (IoT) is becoming increasingly popular in areas like wearable
communication devices, biomedical devices, and home automation systems. IoT-compatible …

Ultralow voltage finFET-versus TFET-based STT-MRAM cells for IoT applications

E Garzón, M Lanuzza, R Taco, S Strangio - Electronics, 2021 - mdpi.com
Spin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic
tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile …

An efficient ultra-low-power and superior performance design of ternary half adder using CNFET and gate-overlap TFET devices

S Vidhyadharan, SS Dan - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This paper presents a novel ultra-low power yet high-performance device and circuit design
paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs …

Boosting the performance of an ultrascaled carbon nanotube junctionless tunnel field-effect transistor using an ungated region: NEGF simulation

K Tamersit - Journal of Computational Electronics, 2019 - Springer
This paper focuses on the role of the longitudinal spacing between the auxiliary gate and
control gate in boosting the performance of an ultrascaled junctionless carbon nanotube …