The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors
(CMPs) will contain hundreds or thousands of cores. Such a many‐core system requires …

Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple
processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) …

The advent of deep sub-micron technology has exacerbated reliability issues in on-chip
interconnects. In particular, single event upsets, such as soft errors, and hard faults are …

Recently, Network-on-Chip (NoC) architectures have gained popularity to address the
interconnect delay problem for designing CMP/multi-core/SoC systems in deep sub-micron …

As technology scales, fault tolerance is becoming a key concern in on-chip communication.
Consequently, this work examines fault tolerant communication algorithms for use in the …

The widespread proliferation of the Chip Multi-Processor (CMP) paradigm has cemented the
criticality of the on-chip interconnection fabric. The Network-on-Chip (NoC) is becoming …

Continuing decrease in the feature size of integrated circuits leads to increases in
susceptibility to transient and permanent faults. This paper proposes a fault-tolerant solution …

The aggressive advent in VLSI manufacturing technology has made dramatic impacts on the
dependability of devices and interconnects. In the modern manycore system, mesh based …

Network-on-Chip (NoC) architectures employing packet-based communication are being
increasingly adopted in System-on-Chip (SoC) designs. In addition to providing high …

Streamlined Design Solutions Specifically for NoCTo solve critical network-on-chip (NoC)
architecture and design problems related to structure, performance and modularity …