Rosetta: A realistic high-level synthesis benchmark suite for software programmable FPGAs
Modern high-level synthesis (HLS) tools greatly reduce the turn-around time of designing
and implementing complex FPGA-based accelerators. They also expose various …
and implementing complex FPGA-based accelerators. They also expose various …
The case for FPGA-based edge computing
Edge Computing has emerged as a new computing paradigm dedicated for mobile
performance enhancement and energy efficiency purposes. Specifically, it benefits today's …
performance enhancement and energy efficiency purposes. Specifically, it benefits today's …
An efficient classification of hyperspectral remotely sensed data using support vector machine
HN Mahendra… - International Journal of …, 2022 - yadda.icm.edu.pl
This work present an efficient hardware architecture of Support Vector Machine (SVM) for
the classification of Hyperspectral remotely sensed data using High Level Synthesis (HLS) …
the classification of Hyperspectral remotely sensed data using High Level Synthesis (HLS) …
Accelerating mobile applications at the network edge with software-programmable FPGAs
Recently, Edge Computing has emerged as a new computing paradigm dedicated for
mobile applications for performance enhancement and energy efficiency purposes …
mobile applications for performance enhancement and energy efficiency purposes …
Analysis and optimization of the implicit broadcasts in FPGA HLS to improve maximum frequency
Designs generated by high-level synthesis (HLS) tools typically achieve a lower frequency
compared to manual RTL designs. In this work, we study the timing issues in a diverse set of …
compared to manual RTL designs. In this work, we study the timing issues in a diverse set of …
Boyi: A systematic framework for automatically deciding the right execution model of OpenCL applications on FPGAs
FPGA vendors provide OpenCL software development kits for easier programmability, with
the goal of replacing the time-consuming and error-prone register-transfer level (RTL) …
the goal of replacing the time-consuming and error-prone register-transfer level (RTL) …
HeteroRefactor: Refactoring for heterogeneous computing with FPGA
Heterogeneous computing with field-programmable gate-arrays (FPGAs) has demonstrated
orders of magnitude improvement in computing efficiency for many applications. However …
orders of magnitude improvement in computing efficiency for many applications. However …
A scalable approach to exact resource-constrained scheduling based on a joint sdc and sat formulation
Despite increasing adoption of high-level synthesis (HLS) for its design productivity
advantage, success in achieving high quality-of-results out-of-the-box is often hindered by …
advantage, success in achieving high quality-of-results out-of-the-box is often hindered by …
A deep-reinforcement-learning-based scheduler for fpga hls
As the most critical stage in FPGA HLS, scheduling depends heavily on heuristics due to
their speed, flexibility, and scalability. However, designing heuristics easily involves human …
their speed, flexibility, and scalability. However, designing heuristics easily involves human …
Design of a real-time face detection architecture for heterogeneous systems-on-chips
Object detection represents one of the most important and challenging task in computer
vision applications. Boosting-based approaches deal with computational intensive …
vision applications. Boosting-based approaches deal with computational intensive …