Rosetta: A realistic high-level synthesis benchmark suite for software programmable FPGAs

Y Zhou, U Gupta, S Dai, R Zhao, N Srivastava… - Proceedings of the …, 2018 - dl.acm.org
Modern high-level synthesis (HLS) tools greatly reduce the turn-around time of designing
and implementing complex FPGA-based accelerators. They also expose various …

The case for FPGA-based edge computing

C Xu, S Jiang, G Luo, G Sun, N An… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Edge Computing has emerged as a new computing paradigm dedicated for mobile
performance enhancement and energy efficiency purposes. Specifically, it benefits today's …

An efficient classification of hyperspectral remotely sensed data using support vector machine

HN Mahendra… - International Journal of …, 2022 - yadda.icm.edu.pl
This work present an efficient hardware architecture of Support Vector Machine (SVM) for
the classification of Hyperspectral remotely sensed data using High Level Synthesis (HLS) …

Accelerating mobile applications at the network edge with software-programmable FPGAs

S Jiang, D He, C Yang, C Xu, G Luo… - … -IEEE Conference on …, 2018 - ieeexplore.ieee.org
Recently, Edge Computing has emerged as a new computing paradigm dedicated for
mobile applications for performance enhancement and energy efficiency purposes …

Analysis and optimization of the implicit broadcasts in FPGA HLS to improve maximum frequency

L Guo, J Lau, Y Chi, J Wang, CH Yu… - 2020 57th ACM/IEEE …, 2020 - ieeexplore.ieee.org
Designs generated by high-level synthesis (HLS) tools typically achieve a lower frequency
compared to manual RTL designs. In this work, we study the timing issues in a diverse set of …

Boyi: A systematic framework for automatically deciding the right execution model of OpenCL applications on FPGAs

J Jiang, Z Wang, X Liu, J Gómez-Luna… - Proceedings of the …, 2020 - dl.acm.org
FPGA vendors provide OpenCL software development kits for easier programmability, with
the goal of replacing the time-consuming and error-prone register-transfer level (RTL) …

HeteroRefactor: Refactoring for heterogeneous computing with FPGA

J Lau, A Sivaraman, Q Zhang, MA Gulzar… - Proceedings of the …, 2020 - dl.acm.org
Heterogeneous computing with field-programmable gate-arrays (FPGAs) has demonstrated
orders of magnitude improvement in computing efficiency for many applications. However …

A scalable approach to exact resource-constrained scheduling based on a joint sdc and sat formulation

S Dai, G Liu, Z Zhang - Proceedings of the 2018 ACM/SIGDA …, 2018 - dl.acm.org
Despite increasing adoption of high-level synthesis (HLS) for its design productivity
advantage, success in achieving high quality-of-results out-of-the-box is often hindered by …

A deep-reinforcement-learning-based scheduler for fpga hls

H Chen, M Shen - 2019 IEEE/ACM International Conference on …, 2019 - ieeexplore.ieee.org
As the most critical stage in FPGA HLS, scheduling depends heavily on heuristics due to
their speed, flexibility, and scalability. However, designing heuristics easily involves human …

Design of a real-time face detection architecture for heterogeneous systems-on-chips

F Spagnolo, S Perri, P Corsonello - Integration, 2020 - Elsevier
Object detection represents one of the most important and challenging task in computer
vision applications. Boosting-based approaches deal with computational intensive …