On the road to 6G: Visions, requirements, key technologies, and testbeds

CX Wang, X You, X Gao, X Zhu, Z Li… - … Surveys & Tutorials, 2023 - ieeexplore.ieee.org
Fifth generation (5G) mobile communication systems have entered the stage of commercial
deployment, providing users with new services, improved user experiences as well as a host …

Flexible polar encoders and decoders

W Gross, G Sarkis, P Giard, C Leroux - US Patent 10,193,578, 2019 - Google Patents
US10193578B2 - Flexible polar encoders and decoders - Google Patents US10193578B2 -
Flexible polar encoders and decoders - Google Patents Flexible polar encoders and …

Flexible and low-complexity encoding and decoding of systematic polar codes

G Sarkis, I Tal, P Giard, A Vardy… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
In this paper, we present hardware and software implementations of flexible polar systematic
encoders and decoders. The proposed implementations operate on polar codes of any …

Channel Coding Towards 6G: Technical Overview and Outlook

M Rowshan, M Qiu, Y **e, X Gu… - IEEE Open Journal of the …, 2024 - ieeexplore.ieee.org
Channel coding plays a pivotal role in ensuring reliable communication over wireless
channels. With the growing need for ultra-reliable communication in emerging wireless use …

Design of hybrid sorting unit

VS Harshini, KKS Kumar - 2019 International Conference on …, 2019 - ieeexplore.ieee.org
Sorting is the fundamental function of any process for most of the application, The widely
used hardware sorting algorithm in VLSI are Bitonic merge sort and Bitonic odd even sort …

High-throughput turbo decoder with parallel architecture for LTE wireless communication standards

R Shrestha, RP Paily - … Transactions on Circuits and Systems I …, 2014 - ieeexplore.ieee.org
This work focuses on the VLSI design aspect of high-speed maximum a posteriori (MAP)
probability decoders which are intrinsic building-blocks of parallel turbo decoders. For the …

High-throughput LDPC-decoder architecture using efficient comparison techniques & dynamic multi-frame processing schedule

S Kumawat, R Shrestha, N Daga… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
This paper presents architecture of block-level-parallel layered decoder for irregular LDPC
code. It can be reconfigured to support various block lengths and code rates of IEEE 802.11 …

A reconfigurable LDPC decoder optimized for 802.11 n/ac applications

I Tsatsaragkos, V Paliouras - IEEE Transactions on Very Large …, 2017 - ieeexplore.ieee.org
This paper presents a high data-rate low-density parity-check (LDPC) decoder, suitable for
the 802.11 n/ac (WiFi) standard. The innovative features of the proposed decoder relate to …

Efficient ldpc encoder design for iot-type devices

J Hyla, W Sułek, W Izydorczyk, L Dziczkowski… - Applied Sciences, 2022 - mdpi.com
Low-density parity-check (LDPC) codes are known to be one of the best error-correction
coding (ECC) schemes in terms of correction performance. They have been utilized in many …

Efficient parallel turbo-decoding for high-throughput wireless systems

C Roth, S Belfanti, C Benkeser… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Turbo decoders for modern wireless communication systems have to support high
throughput over a wide range of code rates. In order to support the peak throughputs …