While research has shown that the agile chip design methodology is promising to sustain
the scaling of computing performance in a more efficient way, it is still of limited usage in …

We present RTL-Repair, a semantics-based repair tool for register transfer level circuit
descriptions. Compared to the previous state-of-the-art tool, RTL-Repair generates more …

Verification of hardware design code is crucial for the quality assurance of hardware
products. Being an indispensable part of verification, localizing bugs in the hardware design …

Since the inception of computing, we have been reliant on CPU-powered architectures.
However, today this reliance is challenged by manufacturing limitations (CMOS scaling) …

Hardware description languages (HDLs) are pivotal for the development of hardware
designs. The programming courses for HDLs are also popular in both universities and …

Developers are turning to heterogeneous computing devices, such as Field Programmable
Gate Arrays (FPGAs), to accelerate data center and cloud computing workloads. FPGAs …

Mutation testing, a well-suited technology for functional validation, is regrettably poorly
studied in hardware. We propose Mantra: the first open-source code-level mutation testing …

This paper establishes the potential of accelerating the evaluation phase of tree-based
genetic programming through contemporary field-programmable gate array (FPGA) …

Since the inception of computing, we have been reliant on CPU-powered architectures.
However, today this reliance is challenged by manufacturing limitations (CMOS scaling) …

High-level programming models for hardware design let domain experts quickly produce
specialized accelerators. However, tools for debugging these accelerators remain tied to low …