This paper introduces a ΔΣ fractional-N digital PLL based on a single-bit TDC. A digital-to-
time converter, placed in the feedback path, cancels out the quantization noise introduced …

This paper presents a 1 V multi-mode RF transceiver for wireless body area network
(WBAN) applications. Operating in the 2.36 GHz Medical Body Area Networks (MBANs) and …

The fundamentals and state of the art in fractional-N phase-locked-loop (PLL)-based
frequency synthesis are reviewed. Particular emphasis is placed on delta-sigma fractional-N …

This paper describes a low power and element-scalable 60 GHz 4-element phased array
transceiver implemented in a standard 65 nm CMOS process. Using a 1.2 V supply, the …

This paper demonstrates that spurious tones in the output of a fractional-N PLL can be
reduced by replacing the DeltaSigma modulator with a new type of digital quantizer and …

A fast-settling adaptive calibration technique is presented that makes phase noise
cancelling DeltaSigma fractional-N PLLs practical for the low reference frequencies …

A frequency synthesizer architecture capable of simultaneously achieving high closed-loop
bandwidth and low output phase noise is presented. The proposed topology uses a …

The increasingly demanding performance requirements of communications systems, as well
as problems posed by the continued scaling of silicon technology, present numerous …

A direct conversion 802.11 a receiver front-end including a synthesizer with quadrature VCO
has been integrated in a 0.13-/spl mu/m CMOS process. The chip has an active area of 1.8 …

The availability of multi-standard terminals will be key to provide location independent
connections able to take advantage of any possible infrastructure. This paper addresses …