From C/C++ code to high-performance dataflow circuits

L Josipović, A Guerrieri, P Ienne - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static
scheduling implies that the resulting circuits have a hard time exploiting parallelism in code …

Svelto: High-level synthesis of multi-threaded accelerators for graph analytics

M Minutoli, VG Castellana, N Saporetti… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
Graph analytics are an emerging class of irregular applications. Operating on very large
datasets, they present unique behaviors, such as fine-grained, unpredictable memory …

High-level synthesis of parallel specifications coupling static and dynamic controllers

VG Castellana, A Tumeo… - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
Conventional High-Level Synthesis (HLS) tools exploit parallelism mostly at the Instruction
Level (ILP). They statically schedule the input specifications and build centralized Finite …

High level synthesis of RDF queries for graph analytics

VG Castellana, M Minutoli, A Morari… - 2015 IEEE/ACM …, 2015 - ieeexplore.ieee.org
In this paper we present a set of techniques that enable the synthesis of efficient custom
accelerators for memory intensive, irregular applications. To address the challenges of …

Efficient synthesis of graph methods: A dynamically scheduled architecture

M Minutoli, VG Castellana, A Tumeo… - 2016 IEEE/ACM …, 2016 - ieeexplore.ieee.org
RDF databases naturally map to a graph representation and employ languages, such as
SPARQL, that implements queries as graph pattern matching routines. Graph methods …

Towards on-chip learning for low latency reasoning with end-to-end synthesis

VG Castellana, NB Agostini, A Limaye… - Proceedings of the 28th …, 2023 - dl.acm.org
The Software Defined Architectures (SODA) Synthesizer is an open-source compiler-based
tool able to automatically generate domain-specialized systems targeting Application …

Automated bug detection for high-level synthesis of multi-threaded irregular applications

P Fezzardi, F Ferrandi - ACM Transactions on Parallel Computing (TOPC …, 2020 - dl.acm.org
Field Programmable Gate Arrays (FPGAs) are becoming an appealing technology in
datacenters and High Performance Computing. High-Level Synthesis (HLS) of multi …

Function calls in high level synthesis

SA Neuendorffer - US Patent 10,671,779, 2020 - Google Patents
(57) ABSTRACT A method of high level synthesis may include detecting in an application,
using computer hardware, a first function including a first call site for a second function and a …

Advanced C++ 14 Multithreading Modelling of Electronics Systems

H Fathollahi - 2022 - webthesis.biblio.polito.it
Chips become more complex so it is so important to have design automation in the upper
level of abstraction, where the trade-off is more effective and functionality is simpler for …

[PDF][PDF] Rapid Prototy** for Hardware Accelerators in the Medical Imaging Domain

M Schmid - 2015 - core.ac.uk
Until around the year 2002, computer architects could rely on Moore's law promising that the
performance of single core general-purpose processors would double every eighteen to …