Embedded multi-die interconnect bridge (EMIB)--a high density, high bandwidth packaging interconnect
R Mahajan, R Sankman, N Patel… - 2016 IEEE 66th …, 2016 - ieeexplore.ieee.org
The EMIB dense MCP technology is a new packaging paradigm that provides localized high
density interconnects between two or more die on an organic package substrate, opening …
density interconnects between two or more die on an organic package substrate, opening …
Embedded multidie interconnect bridge—A localized, high-density multichip packaging interconnect
R Mahajan, Z Qian, RS Viswanath… - IEEE transactions on …, 2019 - ieeexplore.ieee.org
This article provides an overview of the embedded multidie interconnect bridge (EMIB)
multichip packaging (MCP) technology. EMIB is a unique packaging paradigm that provides …
multichip packaging (MCP) technology. EMIB is a unique packaging paradigm that provides …
A 25-gb/s 5-mw cmos cdr/deserializer
JW Jung, B Razavi - IEEE Journal of Solid-State Circuits, 2013 - ieeexplore.ieee.org
The demand for higher data rates in serial links has exacerbated the problem of power
consumption, motivating extensive work on receiver and transmitter building blocks. This …
consumption, motivating extensive work on receiver and transmitter building blocks. This …
Silicon photonic microring links for high-bandwidth-density, low-power chip I/O
Silicon photonic microrings have drawn interest in recent years as potential building blocks
for high-bandwidth off-chip communication links. The authors analyze a terabit-per-second …
for high-bandwidth off-chip communication links. The authors analyze a terabit-per-second …
A 4710 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS
F O'Mahony, JE Jaussi, J Kennedy… - IEEE journal of solid …, 2010 - ieeexplore.ieee.org
A 47× 10 Gb/s chip-to-chip interface consuming 660 mW is demonstrated in 45 nm CMOS.
The circuitry and interconnect are co-designed to minimize power and area for a wide …
The circuitry and interconnect are co-designed to minimize power and area for a wide …
Reducing serial I/O power in error-tolerant applications by efficient lossy encoding
Transferring data between integrated circuits (ICs) accounts for an important fraction of the
power dissipation in wearable and mobile systems. Reducing signal transitions reduces the …
power dissipation in wearable and mobile systems. Reducing signal transitions reduces the …
A 7 Gb/s embedded clock transceiver for energy proportional links
A rapid-on/off transceiver for embedded clock architecture that enables energy proportional
communication over the serial link is presented. In an energy proportional link, energy …
communication over the serial link is presented. In an energy proportional link, energy …
An 8–16 Gb/s, 0.65–1.05 pJ/b, voltage-mode transmitter with analog impedance modulation equalization and sub-3 ns power-state transitioning
Serial link transmitters which efficiently incorporate equalization, while also enabling fast
power-state transitioning to leverage dynamic power scaling, are necessary to meet future …
power-state transitioning to leverage dynamic power scaling, are necessary to meet future …
Receiver Jitter Tracking Characteristics in High‐Speed Source Synchronous Links
High‐speed links which employ source synchronous clocking architectures have the ability
to track correlated jitter between clock and data channels up to high frequencies. However …
to track correlated jitter between clock and data channels up to high frequencies. However …
A True Full-Duplex IO (TFD-IO) With Background SI Cancellation for High-Density Interfaces
S Goyal, G Parulekar, S Gupta - IEEE Transactions on Very …, 2022 - ieeexplore.ieee.org
In this work, we have proposed and experimentally demonstrated a true full-duplex input–
output (TFD-IO) for high-speed high-density interfaces. The proposed TFD-IO can be used …
output (TFD-IO) for high-speed high-density interfaces. The proposed TFD-IO can be used …