Advanced virtual prototy** for cyber-physical systems using RISC-V: implementation, verification and challenges

V Herdt, R Drechsler - Science China Information Sciences, 2022 - Springer
Virtual prototypes (VPs) are crucial in today's design flow. VPs are predominantly created in
SystemC transaction-level modeling (TLM) and are leveraged for early software …

RISC-V based virtual prototype: An extensible and configurable platform for the system-level

V Herdt, D Große, P Pieper, R Drechsler - Journal of Systems Architecture, 2020 - Elsevier
Abstract Internet-of-Things (IoT) opens a new world of possibilities for both personal and
industrial applications. At the heart of an IoT device, the processor is the core component …

Evaluation of dynamic triple modular redundancy in an interleaved-multi-threading risc-v core

M Barbirotta, A Cheikh, A Mastrandrea… - Journal of Low Power …, 2022 - mdpi.com
Functional safety is a key requirement in several application domains in which
microprocessors are an essential part. A number of redundancy techniques have been …

[BOOK][B] Enhanced Virtual Prototy**

RDV Herdt, D Große, R Drechsler - 2021 - Springer
Virtual Prototypes (VPs) play a very important role to cope with the rising complexity in the
design flow of embedded devices. A VP is essentially an executable abstract model of the …

Verifying instruction set simulators using coverage-guided fuzzing

V Herdt, D Große, HM Le… - 2019 Design, Automation …, 2019 - ieeexplore.ieee.org
Verification of Instruction Set Simulators (ISSs) is crucial. Predominantly simulation-based
approaches are used. They require a comprehensive testset to ensure a thorough …

Leveraging the Openness and Modularity of RISC-V in Space

S Di Mascio, A Menicucci, E Gill, G Furano… - Journal of Aerospace …, 2019 - arc.aiaa.org
This paper proposes a roadmap to address present and future needs in space systems with
RISC-V processors. RISC-V is an open and modular instruction set architecture, which is …

Efficient cross-level testing for processor verification: A RISC-V case-study

V Herdt, D Große, E Jentzsch… - 2020 Forum for …, 2020 - ieeexplore.ieee.org
Extensive processor verification at the Register-Transfer Level (RTL) is crucial to avoid bugs.
Therefore, simulation-based approaches are prevalent but they require efficient test …

Fast and accurate performance evaluation for RISC-V using virtual prototypes

V Herdt, D Große, R Drechsler - … & Test in Europe Conference & …, 2020 - ieeexplore.ieee.org
RISC-V is gaining huge popularity in particular for embedded systems. Recently, a SystemC-
based Virtual Prototype (VP) has been open sourced to lay the foundation for providing …

Verifying embedded graphics libraries leveraging virtual prototypes and metamorphic testing

C Hazott, F Stögmüller, D Große - 2024 29th Asia and South …, 2024 - ieeexplore.ieee.org
Embedded graphics libraries are part of the firmware of embedded systems and provide
complex functionalities optimized for specific hardware. After unit testing of embedded …

Towards Specification and Testing of RISC-V ISA Compliance

V Herdt, D Große, R Drechsler - … & Test in Europe Conference & …, 2020 - ieeexplore.ieee.org
Compliance testing for RISC-V is very important. Therefore, an official hand-written
compliance test-suite is being actively developed. However, this requires significant manual …