A special-purpose, hardware-based accelerator may include an input subsystem configured
to receive first and second vectors as operands of a full dot-product operation. The …

Hardware for implementing a Deep Neural Network (DNN) having a convolution layer, the
hardware comprising a plurality of convolution engines each configured to perform …

Method and systems of replacing operations of depthwise separable filters with first and
second replacement convolutional layers are disclosed. Depthwise separable filters …

A general matrix-matrix multiplication (GEMM) dataflow accelerator circuit is disclosed that
includes a smart 3D stacking DRAM architecture. The accelerator circuit includes a memory …

An array-based inference engine includes a plurality of processing tiles arranged in a two-
dimensional array of a plurality of rows and a plurality of columns. Each processing tile …

(57) ABSTRACT A processing unit of an inference engine for machine learning (ML)
includes a first, a second, and a third register, and a matrix multiplication block. The first …

The presently disclosed technology relates to networked control of machine tools. An
example system can use messages as means for transmitting intention and status in a …

Embodiments relate to managing tasks that when executed by a neural processor circuit
instantiates a neural network. The neural processor circuit includes neural engine circuits …

Improvements to graphics processing pipelines are disclosed. More specifically, the vertex
shader stage, which performs vertex transformations, and the hull or geometry shader …

A plurality of hardware accelerators are interconnected and include a special processing
unit and accelerator memory. At least one host computer is coupled to each of the plurality of …